発表 Publication

論文一覧(全て)

456 C. Cheng, K. Shiba, M. Hamada, and T. Kuroda,
"2.5D Integration Using Inductive-Coupling TSV-less Miniature Interposer Achieving 317Gb/s/mm2, 1.2pJ/b Data Transfer,"
JSAP International Conference on Solid State Devices and Materials (SSDM'19), Extended Abstracts, pp. 517-518, Sep. 2019.
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455 K. Shiba, M. Hamada, and T. Kuroda,
"3D SoC Design with TSV-less Power Supply Employing Highly Doped Silicon Via,"
JSAP International Conference on Solid State Devices and Materials (SSDM'19), Extended Abstracts, pp. 515-516, Sep. 2019.
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454 M. Hamada, and T. Kuroda,
"Transmission Line Coupler: High-Speed Interface for Non-Contact Connecter,"
IEICE TRANSACTIONS on Electronics, vol.E102-C, No.7, pp.501-508, July 2019.
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453 T. Tanaka, K. Tabuchi, K. Tatehora, Y. Shiiki, S. Nakagawa, T. Takahashi, R. Shimizu, H. Ishikuro, T. Kuroda, T. Yanagida, and K. Uchida,
"Low-Power and ppm-Level Detection of Gas Molecules by Integrated Metal Nanosheets,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. T158-T159, June 2019.
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452 T. Kuroda,
"3D System Integration in a Package for Artificial Intelligence,"
IEEE Electron Devices Technology and Manufacturing (EDTM’19),
Proc. Tech. Papers, Mar. 2019.
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451 K. Ueyoshi , K. Ando , K. Hirose, S. Takamaeda-Yamazaki, M. Hamada, T. Kuroda, and M. Motomura,
"QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3D SRAM Using Inductive Coupling Technology in 40-nm CMOS,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 54, no. 1, pp. 186-196, Jan. 2019.
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450 R. Shimizu, K. Asako, H. Ojima, S. Morinaga, M. Hamada, and T. Kuroda,
"Balanced Mini-batch Training for Imbalanced Image Data Classification with Neural Network,"
First IEEE International Conference on Artificial Intelligence for Industries (ai4i 2018), Proceedings, pp. 27-30, Sep. 2018.
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449 S. Yanagawa, R. Shimizu, M. Hamada and T. Kuroda,
"Wireless Power Transfer System for 3-D stacked Multiple Receivers Switching between Single and Dual Frequency Modes,"
IEEE International Midwest Symposium on Circuits and Systems, pp. 1046-1049, Aug. 2018.
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448 T. Maruyama, M. Hamada, and T. Kuroda,
"Comparative Performance Analysis of Dual-Rail Domino Logic and CMOS Logic Under Near-Threshold Operation,"
IEEE International Midwest Symposium on Circuits and Systems, pp. 25-28, Aug. 2018.
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447 S. Yanagawa, R. Shimizu, M. Hamada, T. Shimizu, and T. Kuroda,
"Optimization of Resonant Capacitance in Wireless Power Transfer System with 3-D Stacked Two Receivers,"
IEICE Trans. on Electronics, vol. E101-C, no. 7, pp. 488-492, July 2018.
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446 T. Fujimaki, Y. Toeda, M. Hamada, and T. Kuroda,
"An Electrically Small On-Chip Antenna Scaled down to One-Twentyfifth by One-Fiftieth of Wavelength,"
2018 IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting, Proceedings, July 2018.
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445 Y. Toeda, T. Fujimaki, M. Hamada, and T. Kuroda,
"Fully integrated OOK-powered pad-less deep sub-wavelength-sized 5-GHz RFID with on-chip antenna using adiabatic logic in 0.18μm CMOS,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. C27-C28, June 2018.
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444 S. Yanagawa, R. Shimizu, M. Hamada, T. Shimizu, and T. Kuroda,
"Design Methodology in Wireless Power Transfer System for 3-D Stacked Multiple Receivers,"
IEEE International Symposium on Circuits & Systems, May 2018.
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443 K. Ando, K. Ueyoshi, K. Orimo, H. Yonekawa, S. Sato, H. Nakahara, S.
Takamaeda-Yamazaki, M. Ikebe, T. Asai, T. Kuroda, and M. Motomura,
"BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep
Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 53, no. 4, pp. 983-994, Apr.
2018.
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442 板倉洋, 大和田哲, 山田浩利, 吉子尚志, 市川愉, 原口雅嗣, 黒田忠広,
"非接触コネクタを利用した高速伝送の受信端分岐に関する検討,"
電子情報通信学会総合大会, Mar. 2018.
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441 程超然, 宮田知輝, 門本淳一郎, 天野英晴, 黒田忠広,
"ThruChip Interfaceを用いたバスにおける衝突検知,"
情報処理学会 全国大会, Mar. 2018.
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440 柴康太, 宮田知輝, 門本淳一郎, 天野英晴, 黒田忠広,
"ThruChip Interfaceの設計自動化,"
情報処理学会 全国大会, Mar. 2018.
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439 松下悠亮, 小島拓也, 門本淳一郎, 黒田忠広, 天野英晴,
"マルチコア積層システムCube-2の実装と評価,"
情報処理学会 全国大会, Mar. 2018.
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438 門本淳一郎, 宮田知輝, 天野英晴, 黒田忠広,
"ThruChip Interfaceを用いたコア間ネットワーク,"
情報処理学会 全国大会, Mar. 2018.
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437 天野英晴, 宇佐美公良, 黒田忠広, 近藤正章, 中村宏, 並木美太郎, 松谷宏紀,
"ビルディングブロック型計算システムプロジェクトの報告,"
情報処理学会 全国大会, Mar. 2018.
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436 植吉晃大, 安藤洸太, 廣瀨一俊, 高前田伸也, 門本淳一郎, 宮田知輝, 濱田基嗣, 黒田忠広, 本村真人,
"QUEST: A 7.49TOPS Multi-Purpose Log-Quantized DNN Inference Engine
Stacked on 96MB 3D SRAM Using Inductive-Coupling Technology in 40nm
CMOS,"
IEEE SSCS Japan Chapter/Kansai Chapter Technical Seminar, Feb. 2018.
435 K. Ueyoshi, K. Ando, K. Hirose, S. Takamaeda-Yamazaki, J. Kadomoto, T.
Miyata, M. Hamada, T. Kuroda, and M. Motomura,
"QUEST: A 7.49TOPS Multi-Purpose Log-Quantized DNN Inference Engine
Stacked on 96MB 3D SRAM Using Inductive-Coupling Technology in 40nm
CMOS,"
IEEE International Solid-State Circuits Conference (ISSCC'18), Dig. Tech. Papers, pp. 216-217, Feb. 2018.
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434 Akio Nomura, Yusuke Matsushita, Junichiro Kadomoto, Hiroki Matsutani,
Tadahiro Kuroda, and Hideharu Amano,
"Escalator Network for a 3D Chip Stack with Inductive Coupling
ThruChip Interface,"
International Journal of Networking and Computing, vol. 8, no. 1, pp.
124-139, Jan. 2018.
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433 A. Nomura, J. Kadomoto, T. Kuroda, and H. Amano,
"A practical collision avoidance method for an inter-chip bus with wireless
inductive Through Chip Interface,"
International Symposium on Computing and Networking (CANDAR'17),
Conference Paper, Nov. 2017.
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432 J. Kadomoto, H. Amano, and T. Kuroda,
"An Inductive-Coupling Link for 3-D Network-on-Chips,"
14th International SoC Design Conference (ISOCC 2017), Proceedings, pp. 150-151, Nov. 2017.
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431 S. Yanagawa, R. Shimizu, M. Hamada, T. Shimizu, and T. Kuroda,
"Wireless Power Transfer to Stacked Modules for IoT Sensor Nodes,"
14th International SoC Design Conference (ISOCC 2017), Proceedings, pp. 59-60, Nov. 2017.
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430 R. Shimizu, S. Yanagawa, T. Shimizu, M. Hamada, and T. Kuroda,
"Convolutional Neural Network for Industrial Egg Classification,"
14th International SoC Design Conference (ISOCC 2017), Proceedings, pp. 67-68, Nov. 2017.
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429 K. Ando, K. Ueyoshi, K. Orimo, H. Yonekawa, S. Sato, H. Nakahara, M. Ikebe, T. Asai, S. Takamaeda-Yamazaki, T. Kuroda, and M. Motomura,
"BRein Memory: A 13-Layer 4.2 K Neuron/0.8 M Synapse Binary/Ternary Reconfigurable In-Memory Deep Neural Network Accelerator in 65 nm CMOS,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. C24-C25, June 2017.
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428 M. Haraguchi, A. Kosuge, T. Igarashi, S. Masaki, M. Sueda, M. Hamada, and T. Kuroda,
"A 6Gb/s Rotatable Non-Contact Connector with High-Speed/I2C/CAN/SPI Interface Bridge IC,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. C150-C151, June 2017.
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427 黒田忠広,
"左脳・右脳型集積によるモバイル人工知能を目指して,"
半導体産業人協会会報, No.96, pp.8-11, Apr. 2017.
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426 板倉洋, 明星慶洋, 山田浩利, 吉子尚志, 市川愉, 小菅敦丈, 原口雅嗣, 黒田忠広,
"非接触コネクタを利用したケーブル伝送方式の基礎検討,"
電子情報通信学会総合大会, B-4-21, Mar. 2017.
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425 T. Kuroda,
"System Integration in a Package for Cloud and Edge,"
IEEE Electron Devices Technology and Manufacturing (EDTM 2017), Proc. Tech. Papers, pp. 42-43, Mar. 2017.
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424 松下悠亮, 増山滉一朗, 野村明生, 門本淳一郎, 四手井綱章, 黒田忠広, 天野英晴,
"誘導結合ワイヤレスチップ間接続のIP化,"
電子情報通信学会, 信学技報, vol. 116, no. 365, pp. 7-12, Dec. 2016.
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423 A. Nomura, H. Matsutani, T. Kuroda, J. Kadomoto, Y. Matsushita, and H. Amano,
"Vertical Packet Switching Elevator Network Using Inductive Coupling ThruChip Interface,"
International Symposium on Computing and Networking (CANDAR'16), Conference Paper, Nov. 2016.
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422 黒田忠広,
"実装技術の現状と今後の展開,"
ロボット, No.233, pp. 1-2, Nov. 2016.
421 M. Ikebe, T. Asai, M. Mori, T. Itou, D. Uchida, Y. Take, T. Kuroda, and M. Motomura,
"3D stacked image sensor featuring low noise inductive coupling channels,"
3rd International Workshop on Image Sensors and Imaging Systems (IWISS2016), pp. 15-16, Nov. 2016.
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420 門本淳一郎, 宮田知輝, 天野英晴, 黒田忠広,
"An Inductive-Coupling Bus with Collision Detection Scheme Using Magnetic Field Variation for 3-D Network-on-Chips,"
IEEE SSCS Japan/Kansai Chapter A-SSCC報告会, Nov. 2016.
419 J. Kadomoto, T. Miyata, H. Amano, and T. Kuroda,
"An Inductive-Coupling Bus with Collision Detection Scheme Using Magnetic Field Variation for 3-D Network-on-Chips,"
IEEE Asian Solid-State Circuits Conference (A-SSCC 2016), Proc. Tech. Papers, pp. 41-44, Nov. 2016.
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418 R. Shimizu, S.Yanagawa, Y. Monde, H. Yamagishi, M. Hamada, T. Shimizu, and T. Kuroda,
"Deep Learning Application Trial to Lung Cancer Diagnosis for Medical Sensor Systems,"
13th International SoC Design Conference (ISOCC 2016), Proceedings, pp. 194-195, Oct. 2016.
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417 Ahmad Muzaffar bin Baharudin, Mika Saari, Pekka Sillberg, Petri Rantanen, Jari Soini, and Tadahiro Kuroda,
"Low-Energy Algorithm for Self-Controlled Wireless Sensor Nodes,"
The International Conference on Wireless Networks and Mobile Communications (WINCOM’16), Conference Paper, Oct. 2016.
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416 H. Itakura, Y. Akeboshi, H. Yamada, H. Yoshiko, S. Ichikawa, A. Kosuge, M. Haraguchi, T. Kuroda,
"Basic Study of Non-Contact Connector for High-Speed Space Cable Transmission,"
International SpaceWire Conference (ISC 2016), Short Paper, Oct. 2016.
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415 S. Hasegawa, J. Kadomoto, A. Kosuge, and T. Kuroda,
"A 1 Tb/s/mm2 Inductive-Coupling Side-by-Side Chip Link,"
European Solid-State Circuits Conference (ESSCIRC 2016), pp. 469-472, Sep. 2016.
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414 J. Kadomoto, S. Hasegawa, Y. Kiuchi, A. Kosuge, and T. Kuroda,
"Analysis and Evaluation of Electromagnetic Interference between ThruChip Interface and LC-VCO,"
IEICE Trans. on Electronics, vol. E99-C, no. 6, pp. 659-662, June 2016.
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413 長谷川蒼, 新谷悟, 中野慎也, 加藤智, 黒田忠広,
"コンタクトイメージセンサ向けの小面積高速オペアンプ,"
電子回路研究会, June 2016.
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412 A. Kosuge, J. Kadomoto, and T. Kuroda,
"A 6 Gb/s 6 pJ/b 5mm-Distance Non-Contact Interface for Modular Smartphones Using Two-Fold Transmission Line Coupler and High EMC Tolerant Pulse Transceiver,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 51, no. 6, pp. 1446-1456, June 2016.
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411 T. Kuroda,
"Near-Field Coupling Integration Technology,"
ECS Transactions, 72(3) 83-91, May 2016.
410 黒田忠広,
"ICの物語,"
パリティ Vol.31 No.02, 丸善出版, Feb. 2016.
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409 A. Kosuge, J. Hashiba, T. Kawajiri, S. Hasegawa, T. Shidei, H.Ishikuro, T. Kuroda, and K. Takeuchi,
"An Inductively-Powered Wireless Solid-State Drive System with Merged Error Correction of High-Speed Wireless Data Links and NAND Flash Memories,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 51, no. 4, pp. 1041-1050, Apr. 2016.
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408 T. Kuroda,
"Near-Field Coupling Integration Technology,"
IEEE International Solid-State Circuits Conference (ISSCC'16), Dig. Tech.
Papers, pp. 502-505, Feb. 2016.
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407 A. Kosuge, A. Okada, M. Taguchi, H. Ishikuro, and T. Kuroda,
“A 280Mb/s In-Vehicle LAN System Using Electromagnetic Clip Connector and High-EMC Transceiver,”
IEEE Transactions on Circuits and Systems-I: Regular Papers (TCAS-I), vol. 63, no. 2, pp. 265-275, Feb. 2016.
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406 T. Kagami, H. Matsutani, M. Koibuchi, Y. Take, T. Kuroda, H. Amano,
"Efficient 3-D Bus Architecture for Inductive-Coupling ThruChip Interface,"
IEEE Transaction on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 2, pp. 493-506, Feb. 2016.
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405 L. Hsu, J. Kadomoto, S. Hasegawa, A. Kosuge, Y. Take, and T. Kuroda,
"Analytical ThruChip Inductive Coupling Channel Design Optimization,"
2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 731-736, Jan. 2016.
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404 L. Hsu, J. Kadomoto, S. Hasegawa, A. Kosuge, Y. Take, and T. Kuroda,
"A Study of Physical Design Guidelines in ThruChip Inductive Coupling Channel,"
IEICE Trans. on Fundamentals, vol. E98-A, no. 12, pp. 2584-2591, Dec. 2015.
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403 黒田忠広,
"半導体ディジタルロゼッタストーン,"
電子情報通信学会誌, vol. 98, no. 12, pp. 1057-1062, Dec. 2015.
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402 門出康孝,山岸裕樹,花井陽介,清水徹,黒田忠広,
"ヒトの尿データへのDeepLearning適用による肺がん判定の試行と標的物質の探索,"
第106回 知識ベースシステム研究会 (SIG-KBS), Nov. 2015.
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401 Y. Take, J. Kadomoto, and T. Kuroda,
"3D Integration Using Inductive Coupling and Coupled Resonator,"
in Proc. IEEE International Symposium on Radio-Frequency Integration Technology (RFIT'15), pp. 46-48, Aug. 2015.
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400 黒田忠広,
"LEGO型コンピューター実現へ,"
日経エレクトロニクス8月号 , pp. 59-68, Aug. 2015.
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399 A. Kosuge, S. Ishizuka, M. Taguchi, H. Ishikuro, and T. Kuroda,
"Analysis and Design of an 8.5-Gb/s/link Multi-Drop Bus Using Energy-Equipartitioned Transmission Line Couplers,"
IEEE Transactions on Circuits and Systems-I: Regular Papers (TCAS-I), vol. 62, no. 8, pp. 2122-2131, Aug. 2015.
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398 黒田忠広,
""脳"の省電力性能を目指して,"
日経エレクトロニクス7月号, pp. 91-98, July 2015.
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397 M. Ikebe, D. Uchida, Y. Take, M. Someya, S. Chikuda, K. Matsuyama, T. Asai, T. Kuroda, and M. Motomura,
"Image Sensor/Digital Logic 3D Stacked Module Featuring Inductive Coupling Channels for High Speed/Low-Noise Image Transfer,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. C82-C83, June 2015.
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396 A. Kosuge, J. Hashiba, T. Kawajiri, S. Hasegawa, T. Shidei, H.Ishikuro, T. Kuroda, and K. Takeuchi,
"Inductively-Powered Wireless Solid-State Drive (SSD) System with Merged Error Correction of High-Speed Non-Contact Data Links and NAND Flash Memory,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. C128-C129, June 2015.
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395 門出康孝,清水徹,黒田忠広,
"ヒトの尿データへのDeepLearning適用による肺がん判定の試行と考察"
2015年度人工知能学会全国大会(第29回),Jun. 2015.
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394 Y. Take, T. Kuroda,
"Relay Transmission Thruchip Interface with Low-Skew 3D Clock Distribution Network,"
IEICE TRANSACTIONS on Electronics, vol. E98-C, no. 4, pp. 322-332, May 2015.
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393 小菅敦丈, 石塚秀, 門本淳一郎, 黒田忠広,
"A 6Gb/s 6pJ/b 5mm-Distance Non-Contact Interface for Modular Smartphones
Using Two-Fold Transmission Line Coupler and EMC-Qualified Pulse Transceiver,"
IEEE SSCS Japan/Kansai Chapter ISSCC報告会, Mar. 2015.
392 A. Kosuge, S. Ishizuka, M. Abe, S. Ichikawa, and T. Kuroda,
"A 6.5Gb/s Shared Bus using Electromagnetic Connectors for Downsizing and Lightening Satellite Processor System by 60%,"
IEEE International Solid-State Circuits Conference (ISSCC'15), Dig. Tech. Papers, pp. 434-435, Feb. 2015.
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391 A. Kosuge, S. Ishizuka, J. Kadomoto, and T. Kuroda,
"A 6Gb/s 6pJ/b 5mm-Distance Non-Contact Interface for Modular Smartphones Using Two-Fold Transmission Line Coupler and EMC-Qualified Pulse Transceiver,"
IEEE International Solid-State Circuits Conference (ISSCC'15), Dig. Tech. Papers, pp. 176-177, Feb. 2015.
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390 L. Hsu, Y. Take, A. Kosuge, S. Hasegawa, J. Kadomoto, and T. Kuroda,
"Design and Analysis for ThruChip Design for Manufacturing (DFM),"
20th Asia and South Pacific Design Automation Conference (ASP-DAC'15), Proceedings, pp. 46-47, Jan. 2015.
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389 A. Okada, A. Raziz Junaidi, Y. Take, A. Kosuge, and T. Kuroda,
"Circuit and Package Design for 44GB/s Inductive-Coupling DRAM/SoC Interface,"
20th Asia and South Pacific Design Automation Conference (ASP-DAC'15), Proceedings, pp. 44-45, Jan. 2015.
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388 T. Kuroda,
"Circuit and Device Interactions for 3D Integration Using Inductive Coupling,"
IEEE International Devices Meeting (IEDM 2014), Proc. Tech. Papers,
18.6.1-18.6.4, Dec. 2014.
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387 A. Raziz Junaidi, Y. Take, and T. Kuroda,
"An Inductive-Coupling Memory/Processor Interface Using Overlapping Coils with Phase Division Multiplexing and Ultra-Thin Fan-Out Wafer Level Package,"
Malaysia-Japan Academic Scholar Conference(MJASC), Session M14-P18-A, Nov. 2014.
386 岡田晃, 小菅敦丈, 黒田忠広,
"近接場結合を用いたLSIとモジュールの三次元集積,"
電子情報通信学会論文誌, pp. 378-385, Nov. 2014.
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385 T. Kuroda,
"3D Integration by Inductive Coupling,"
Proc. IEEE Custom Integrated Circuits Conf. (CICC), Session 11-3, Sep. 2014.
384 D. Ditzel, T. Kuroda, and S. Lee,
"Low-Cost 3D Chip Stacking with ThruChip Wireless Connections,"
Hot Chips - A Symposium on High Performance Chips, Aug. 2014.
383 岡田晃, 小菅敦丈, 石塚秀, 劉楽昌, 田口眞男, 石黒仁揮, 黒田忠広,
"車載LAN向け非接触コネクタ及び高ノイズ耐性送受信回路,"
電子情報通信学会技術研究報告, pp. 23-27, Oct. 2014.
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382 A. Raziz Junaidi, Y. Take, and T. Kuroda,
"A 352Gb/s Inductive-Coupling DRAM/SoC Interface Using Overlapping Coils with Phase Division Multiplexing and Ultra-Thin Fan-Out Wafer Level Package,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. 29-30, June 2014.
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381 小菅敦丈, 石塚秀, 劉楽昌, 岡田晃, 田口眞男, 石黒仁揮, 黒田忠広,
"An Electromagnetic Clip Connector for In-Vehicle LAN to Reduce Wire Harness Weight by 30%,"
IEEE SSCS Japan/Kansai Chapter ISSCC報告会, May. 2014.
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380 Y. Take, H. Matsutani, D. Sasaki, M. Koibuchi, T. Kuroda, H. Amano,
"3-D NoC with Inductive-Coupling Links for Building-Block SiPs,"
IEEE Transactions on Computers, vol. 63, no. 3, pp. 748-763, Mar. 2014.
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379 A. Kosuge, S. Ishizuka, L. Liu, A. Okada, M. Taguchi, H. Ishikuro, and T. Kuroda,
"An Electromagnetic Clip Connector for In-Vehicle LAN to Reduce Wire Harness Weight by 30%,"
IEEE International Solid-State Circuits Conference (ISSCC'14), Dig. Tech. Papers, pp. 496-497, Feb. 2014.
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378 A. Kosuge, W. Mizuhara, T. Shidei, T. Takeya, N. Miura, M. Taguchi, H. Ishikuro, and T. Kuroda,
"A 0.15-mm-Thick Noncontact Connector for MIPI Using a Vertical Directional Coupler,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 49, no. 1, pp. 223-231, Jan. 2014.
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377 小菅敦丈,
"前回最優秀賞の受賞者がRohde & Schwarz本社を訪問,"
日経エレクトロニクス12月23日号, pp. 45-47, Dec. 2013.
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376 黒田忠広,
"実装インタコネクトの課題,"
日本信頼性学会誌, vol. 35, no. 8, p. 469, Dec. 2013.
375 黒田忠広,
"非接触インタコネクトのアプリケーション,"
日本信頼性学会誌, vol. 35, no. 8, p. 473, Dec. 2013.
374 K. Ohata, Y. Sanada, T. Ogaki, K. Matsuyama, T. Ohira, S. Chikuda, M. Igarashi, M. Ikebe, T. Asai, M. Motomura, and T. Kuroda,
"Hardware-Oriented Stereo Vision Algorithm based on 1-D Guided Filtering and its FPGA Implementation,"
IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 169-172, Dec. 2013.
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373 N. Miura, Y. Koizumi, E. Sasaki, Y. Take, H. Matsutani, T. Kuroda, H. Amano, R. Sakamoto, M. Namiki, K. Usami, M. Kondo, H. Nakamura,
"A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface,"
IEEE Micro, Vol.33, No.6, pp.6-15, Dec 2013.
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372 小菅敦丈,
"近接場電磁界を用いた非接触通信技術を開発,"
日経エレクトロニクス12月9日号, pp. 51-53, Dec. 2013.
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371 A. Kosuge,
"Wireless Interconnect Technology by Near-Filed Coupling,"
Nikkei Electronics Award Trip at Rohde & Schwarz, Oct. 2013.
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370 小菅敦丈,
"ワイヤレスSSDに向けた高速通信技術,"
CEATEC 2013 NE シアター, Oct. 2013.
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369 Y. Miyahara, K. Ishikawa, and T. Kuroda,
"A Sub-threshold Region Operating Ultra-low Power 2.4GHz VCO and Frequency Divider,"
JSAP International Conference on Solid State Devices and Materials (SSDM'13), Sep. 2013.
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368 Y. Ono, A. Raziz, and T. Kuroda,
"Adaptive Window Search Using Semantic Texton Forests For Real-time Object Detection,"
IEEE International Conference on Image Processing (ICIP), Sep. 2013.
pdf
367 N. Miura, Y. Koizumi, E. Sasaki, Y. Take, H. Matsutani, K. Usami, T. Kuroda,
H. Amano, R. Sakamoto, M. Namiki, K. Usami, M. Kondo, and H. Nakamura,
"A Scalable 3D Heterogeneous Multi-Core Processor with Inductive-Coupling ThruChip Interface,"
Hot Chips - A Symposium on High Performance Chips, Aug. 2013
366 小菅敦丈, 水原渉, 四手井綱章, 竹谷勉, 三浦典之, 田口眞男, 石黒仁揮, 黒田忠広,
"方向性結合器を用いた携帯機器用途向け0.15mm厚非接触コネクタ,"
シリコン材料・デバイス研究会(SDM)/集積回路研究会(ICD), Aug. 2013.
pdf
365 N. Lu, K. Chang, F. Chang, T. Kuroda, K. Matsudera, L. Madden, S. Borkar, T. Pawlowski, K. Sohn, E. Tsern,
"The Best Logic and Memory Interface Technology for 2D/2.5D/3D ICs,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp.C177-C178, June 2013.
pdf
364 K. Yoshioka, A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro,
"A 0.0058mm2 7.0 ENOB 24MS/s 17fJ/conv. Threshold Configuring SAR ADC with Source Voltage Shifting and Interpolation Technique,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. C266-C267, June 2013.
pdf
363 L. Liu, K. Ishikawa, and T. Kuroda,
"A 720uW 873MHz-1.008GHz Injection-Locked Frequency Multiplier with 0.3V Supply Voltage in 90nm CMOS,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. C140-C141, June 2013.
pdf
362 M. Nomura, A. Muramatsu, H. Takeno, S. Hattori, D. Ogawa, M. Nasu, K.Hirairi, S. Kumashiro,
S. Moriwaki, Y. Yamamoto, S. Miyano, Y. Hiraku, I.Hayashi, K. Yoshioka, A. Shikata, H. Ishikuro, M. Ahn, Y. Okuma, X. Zhang,Y. Ryu, K. Ishida, M. Takamiya, T. Kuroda, H. Shinohara, and T. Sakurai,
"0.5V Image Processor with 563 GOPS/W SIMD and 32bit CPU Using High Voltage Clock Distribution (HVCD) and Adaptive Frequency Scaling (AFS) with 40nm CMOS,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. C36-C37, June 2013.
pdf
361 小菅敦丈,
"ワイヤレスSSDに向けた高速通信技術,"
NE ジャパン・ワイヤレス・テクノロジー・アワード 2013, May 2013.
pdf
360 T. Takeya, and T. Kuroda,
"Transmission Line Coupler Design and Mixer-Based Receiver for Dicode Partial Response Communications,"
IEICE TRANS. FUNDAMENTALS, vol. E96-A, no. 5, pp. 940-946, May 2013.
pdf
359 A. Kosuge, T. Takeya, M. Shioya, M. Taguchi, and T. Kuroda,
"A 3 Gbps Non-Contact Inter-Module Link with Twofold Transmission Line Couplers and Low Frequency Compensation Equalizer,"
Japanese Journal of Applied Physics (JJAP), vol. 52, no. 4, Apr. 2013.
pdf
358 T. Takeya, L. Nan, S. Nakano, N. Miura, H. Ishikuro, and T. Kuroda,
"A 12-Gb/s non-contact interface with coupled transmission lines,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 48, no. 3, pp. 790-800, Mar. 2013.
pdf
357 T. Takeya, and T. Kuroda,
"Symbol-Rate Clock Recovery for Integrating DFE Receivers,"
IEICE Trans. on Fundamentals, vol. E96-A, no. 3, pp. 705-712, Mar. 2013.
pdf
356 A. Shikata, R. Sekimoto, K. Yoshioka, T. Kuroda, and H. Ishikuro,
"A 4-10bit, 0.4-1V Power Supply, Power Scalable Asynchronous SAR-ADC in 40nm-CMOS with Wide Supply Voltage Range SAR Controller,"
IEICE Trans. on Fundamentals, vol. E96-A, no. 2, Feb. 2013.
pdf
355 W. Mizuhara, T. Shidei, A. Kosuge, T. Takeya, N. Miura, M. Taguchi, H. Ishikuro, and T. Kuroda,
"A 0.15mm-Thick Non-Contact Connector for MIPI Using Vertical Directional Coupler,"
IEEE International Solid-State Circuits Conference (ISSCC'13), Dig. Tech. Papers, pp. 200-201, Feb. 2013.
pdf
354 H. Fukuda, T. Terada, and T. Kuroda,
"Retrodirective Transponder Array with Universal On-Sheet Reference for Wireless Mobile Sensor Networks Without Battery or Oscillator,"
IEEE International Solid-State Circuits Conference (ISSCC'13), Dig. Tech. Papers, pp. 204-205, Feb. 2013.
pdf
353 N. Miura, M. Saito, M. Taguchi, and T. Kuroda,
"A 6nW Inductive-Coupling Wake-Up Transceiver for Reducing Standby Power of Non-Contact Memory Card by 500x,"
IEEE International Solid-State Circuits Conference (ISSCC'13), Dig. Tech. Papers, pp. 214-215, Feb. 2013.
pdf
352 Y. Take, N. Miura, H. Ishikuro, and T. Kuroda,
"3D Clock Distribution Using Vertically/Horizontally Coupled Resonators,"
IEEE International Solid-State Circuits Conference (ISSCC'13), Dig. Tech. Papers, pp. 258-259, Feb. 2013.
pdf
351 H. Matsutani, P. Bogdan, R. Marculescu, Y. Take, D. Sasaki, H. Zhang, M. Koibuchi, T. Kuroda, and H. Amano,
"A Case for Wireless 3D NoCs for CMPs,"
18th Asia and South Pacific Design Automation Conference (ASP-DAC'13), Proceedings, pp. 23-28, Jan. 2013.
pdf
350 K. Yoshioka, A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro,
"A 0.35-0.8V 8b 0.5-35MS/s 2bit/step Extremely-low Power SAR ADC,"
18th Asia and South Pacific Design Automation Conference (ASP-DAC'13), Proceedings, pp. 111-112, Jan. 2013.
pdf
349 A. Kosuge, W. Mizuhara, N. Miura, M. Taguchi, H. Ishikuro, and T. Kuroda,
"A 12.5Gb/s/Link Non-Contact Multi-Drop Bus System with Impedance-Matched Transmission Line Couplers and Dicode Partial-Response Channel Transceivers,"
18th Asia and South Pacific Design Automation Conference (ASP-DAC'13), Proceedings, pp. 91-92, Jan. 2013.
pdf
348 Y. Koizumi, H. Amano, H. Matsutani, N. Miura, T. Kuroda, R. Sakamoto, M. Namiki, K. Usami, M. Kondo, and H. Nakamura, "Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect,"
International Conference on Field-Programmable Technology (ICFPT'12), pp. 293-296, Dec 2012.
pdf
347 K. Tomita, R. Shinoda, T. Kuroda, and H. Ishikuro,
"1-W 3.3–16.3-V Boosting Wireless Power Transfer Circuits With Vector Summing Power Controller,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 47, no. 11, pp. 2576-2585, Nov. 2012.
pdf
346 R. Sekimoto, A. Shikata, K. Yoshioka, T. Kuroda, and H. Ishikuro,
"A 40nm CMOS Full Asynchronous Nano-Watt SAR ADC with 98% Leakage Power
Reduction by Boosted Self Power Gating,"
IEEE Asian Solid-State Circuits Conference (A-SSCC'12), Proc. Tech. Papers, pp. 161-164, Nov. 2012.
pdf
345 Y. Hiraku, I. Hayashi, H. Chung, T. Kuroda, and H. Ishikuro,
"A 0.5V 10MHz-to-100MHz 0.47µW/MHz Power Scalable Ad-PLL in 40nm CMOS,"
IEEE Asian Solid-State Circuits Conference (A-SSCC'12), Proc. Tech. Papers, pp. 33-36, Nov. 2012.
pdf
344 T. Kuroda,
"ThruChip interface for heterogeneous chip stacking,"
ECS Transactions, vol. 14, no. 50, pp. 63-68, Oct. 2012.
343 H. Chung, A. Radecki, N. Miura, H. Ishikuro, and T. Kuroda,
"A 0.025–0.45 W 60%-Efficiency Inductive-Coupling Power Transceiver With 5-Bit Dual-Frequency Feedforward Control for Non-Contact Memory Cards,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 47, no. 10, pp. 2496-2504, Oct. 2012.
pdf
342 M. Saito, N. Miura, and T. Kuroda,
"Analysis and Design of Coil with Feed Line for ThruChip Interface,"
JSAP International Conference on Solid State Devices and Materials (SSDM'12), Extended Abstracts, pp. 1160-1161, Sep. 2012.
pdf
341 A. Kosuge, T. Takeya, M. Shioya, M. Taguchi, and T. Kuroda,
"A 3Gb/s Non-Contact Inter-Module Link with Duplex Transmission-Line-Couplers and Low-Frequency Compensation Equalizer,"
JSAP International Conference on Solid State Devices and Materials (SSDM'12), Extended Abstracts, pp. 1152-1153, Sep. 2012.
pdf
340 A. Kosuge, W. Mizuhara, N. Miura, M. Taguchi, H. Ishikuro, and T. Kuroda,
"A 12.5Gb/s/Link Non-Contact Multi Drop Bus System with Impedance-Matched Transmission Line Couplers and Dicode Partial-Response Channel Transceivers,"
in Proc. IEEE Custom Integrated Circuits Conf. (CICC), pp. 7.9.1-7.9.4, Sep. 2012.
pdf
339 L. Liu, H. Ishikuro, and T. Kuroda,
"A 100Mb/s 13.7pJ/bit DC-960MHz Band Plesiochronous IR-UWB Receiver with Costas-Loop Based Synchronization Scheme in 65nm CMOS,"
in Proc. IEEE Custom Integrated Circuits Conf. (CICC), pp. 8.6.1-8.6.4, Sep. 2012.
pdf
338 X. Zhu, Y. Chen, S. Tsukamoto and T. Kuroda,
"A 9-bit 100MS/s SARADC with Digitally Assisted Background Calibration,"
IEICE Trans. on Electronics, vol. E95-C, no. 6, pp. 1026 -1034, June 2012.
pdf
337 N. Miura, M. Saito, and T. Kuroda,
"A 1TB/s 1pJ/b 6.4mm2/TB/s QDR Inductive-Coupling Interface Between 65-nm CMOS Logic and Emulated 100-nm DRAM,"
IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol. 2, no. 2, pp.249-256, June 2012.
pdf
336 黒田忠広,
"近接場ワイヤレス通信が拓く三次元実装,"
エレクトロニクス実装学会誌, vol. 15, no. 4, pp. 231-235, May 2012.
pdf
335 T. Kuroda,
"Near-Field Wireless Connection for 3D-System Integration,"
IEEE Symposium on VLSI Technology, Dig. Tech. Papers, pp. 105-106, June 2012.
pdf
334 Y. Shimazaki, N. Miura, and T. Kuroda,
"A 5.184Gbps/ch Through-Chip Interface and Automated Place-and-Route Design Methodology for 3-D Integration of 45nm CMOS Processors,"
IEEE Symposium on low-Power and High-Speed Chips (COOL Chips) XV, Apr. 2012.
pdf
333 H. Chung, H. Ishikuro, and T. Kuroda,
"A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 47, no. 5, pp. 1232-1241, May. 2012.
pdf
332 X. Zhu, Y. Chen, S. Tsukamoto, T. Kuroda,
" A 9-bit 100MS/s Tri-level Charge Redistribution SAR ADC with Asymmetric CDAC Array,"
2012 International Symposium on VLSI Design, Automation and Test (2012 VLSI-DAT), Hsinchu, Taiwan, Apr. 2012.
pdf
331 M. Saito, N. Miura, and T. Kuroda,
"Asynchronous Pulse Transmitter for Power Reduction in Inductive-Coupling Link,"
Japanese Journal of Applied Physics(JJAP), vol. 51 No. 2, Apr. 2012.
pdf
330 A. Radecki, H.Chung, Y. Yoshida, N. Miura, T. Shidei, H. Ishikuro and T. Kuroda,
"6W/25mm2 Wireless Power Transmission for Non-contact Wafer-Level Testing,"
IEICE Trans. on Electronics, vol. E95-C, No. 4, pp. 668-676, Apr. 2012.
pdf
329 A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro,
"A 0.5 V 1.1 MS/sec 6.3 fJ/conversion-step SAR-ADC with tri-level comparator in 40 nm CMOS,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 47, no. 4, pp. 1022-1030, Apr. 2012.
pdf
328 H. Zhang, H. Matsutani, Y. Take, T. Kuroda, and H. Amano,
"Vertical Link On/Off Control Methods for Wireless 3-D NoCs,"
Proc. of the 25th International Conference on Architecture of Computing Systems (ARCS'12), pp. 212-224, Feb 2012.
327 W. Yun, S. Nakano, W. Mizuhara, A. Kosuge, N. Miura, H. Ishikuro, and T. Kuroda,
"A 7Gb/s/Link Non-Contact Memory Module for Multi-Drop Bus System Using Energy-Equipartitioned Coupled Transmission Line,"
IEEE International Solid-State Circuits Conference (ISSCC'12), Dig. Tech. Papers, pp. 52-53, Feb. 2012.
pdf
326 T. Abe, Y. Yuan, H. Ishikuro, and T. Kuroda,
"A 2Gb/s 150mW UWB Direct-Conversion Coherent Transceiver with IQ-Switching Carrier-Recovery Scheme,"
IEEE International Solid-State Circuits Conference (ISSCC'12), Dig. Tech. Papers, pp. 442-443, Feb. 2012.
pdf
325 Y. Take, H. Chung, N. Miura, and T. Kuroda,
"Simultaneous Data and Power Transmission using Nested Clover Coils,"
17th Asia and South Pacific Design Automation Conference (ASP-DAC'12), Proceedings, pp. 555-556, Jan. 2012.
pdf
324 黒田忠広,
"磁界結合による無線インタコネクション技術,"
電子情報通信学会誌, vol. 94, no. 12, pp. 1041-1045, Dec. 2011.
pdf
323 T. Kuroda,
"Proximity IOs Using Inductive Coupling,"
IEEE International Symposium on Radio-Frequency Integration Technology (RFIT'11), pp. 37-40, Nov. 2011.
pdf
322 T. Kuroda,
"How to write a good ISSCC paper (Tutorial),"
IEEE Asian Solid-State Circuits Conference (A-SSCC'11), Nov. 2011.
321 K. Tomita, R. Shinoda, T. Kuroda, and H. Ishikuro,
"1W 3.3V-to-16.3V Boosting Wireless Power Transfer Circuits with Vector Summing Power Controller,"
IEEE Asian Solid-State Circuits Conference (A-SSCC'11), Proc. Tech. Papers, pp. 177-180, Nov. 2011.
pdf
320 A. Radecki, N. Miura, H. Ishikuro, and T. Kuroda,
"Rotary coding for power reduction and S/N improvement in inductive-coupling data communication,"
IEEE Asian Solid-State Circuits Conference (A-SSCC'11), Proc. Tech. Papers, pp. 205-208, Nov. 2011.
pdf
319 W-J. Yun, H. Ishikuro, and T. Kuroda,
"A 0.6V Noise Rejectable All-Digital CDR with Free Running TDC for a Pulse-Based Inductive-Coupling Interface,"
IEEE Asian Solid-State Circuits Conference (A-SSCC'11), Proc. Tech. Papers, pp. 145-148, Nov. 2011
pdf
318 N. Miura,
"Non-Contact Interface for 3D Memory System (Tutorial),"
IEEE Asian Solid-State Circuits Conference (A-SSCC'11), Nov. 2011.
317 三浦典之,
"側壁絶縁シリコンチップ試作,"
ナノテクノロジー・ネットワーク平成23年度成果報告会, Nov. 2011.
316 Y. Take, N. Miura, and T. Kuroda,
"A 30Gb/s/Link 2.2Tb/s/mm2 inductively-coupled injection-locking CDR for high-speed DRAM interface,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 46, no. 11, pp. 2552-2559, Nov. 2011.
pdf
315 K. Niitsu, Y. Sugimori, Y. Kohama, K. Osada, N. Irie, H. Ishikuro and T. Kuroda,
"Analysis and Techniques for Mitigating Interface From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration,"
IEEE Transaction on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 10, Oct. 2011.
pdf
314 T. Kuroda,
"ThruChip Interface (TCI) for 3D Networks on Chip,"
2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, pp. 238-241, Oct. 2011.
pdf
313 M. Saito, N. Miura, and T. Kuroda,
"Asynchronous Pulse Transmitter for Power Reduction in ThruChip Interface,"
International Conference on Solid-State Devices and Materials (SSDM), Sep. 2011.
pdf
312 R. Sekimoto, A. Shikata, T. Kuroda, and H. Ishikuro,
"A 40nm 50S/s - 8MS/s Ultra Low Voltage SAR ADC with Timing Optimized Asynchronous Clock Generator,"
2011 European Solid-State Circuits Conference (ESSCIRC'11), Dig. Tech. Papers,
pp. 12-16, Sep. 2011.
pdf
311 J. Nishimura and T. Kuroda,
"Human Action Recognition Using Wireless Wearable In-Ear Microphone,"
IEEJ, vol.131, no.9, Sec.C, pp.1570-1576, 2011.
pdf
310 小野友己, 黒田忠広,
"顔検出における識別コストの削減および検出精度向上のための特徴分割SVM,"
MIRU2011 画像の理解・認識シンポジウム, July 2011.
309 A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro,
"A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with Tri-Level Comparator in 40nm CMOS,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. 262-263, June 2011.
pdf
308 H. Ishizaki, H. Ikeda, Y. Yoshida, T. Maeda, T. Kuroda, and M. Mizuno,
"A Battery-less WiFi-BER modulated data transmitter with ambient radio-wave energy harvesting,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. 162-163, June 2011.
pdf
307 黒田忠広,
"自然界の集団同期現象をエレクトロニクスに応用,"
日経エレクトロニクス6月13日号, pp. 85-94, June 2011.
306 竹谷勉, Nan Lan, 中野慎也, 三浦典之, 石黒仁揮, 黒田忠広,
"A 12Gb/s Non-Contact Interface with Coupled Transmission Lines,"
IEEE SSCS Kansai Chapter Technical Seminar, May 2011.
305 H. Matsutani, Y. Take, D. Sasaki, M. Kimura, Y. Ono, Y. Nishiyama, M. Koibuchi, T. Kuroda, and H. Amano,
"A Vertical Bubble Flow Network using Inductive-Coupling for 3-D CMPs,"
Proc. of the 5th ACM/IEEE International Symposium on Networks-on-Chip (NOCS'11), pp. 49-56, May 2011.
pdf
304 竹谷勉, Nan Lan, 中野慎也, 三浦典之, 石黒仁揮, 黒田忠広,
"A 12Gb/s Non-Contact Interface with Coupled Transmission Lines,"
集積回路研究会(ICD), Apr. 2011.
pdf
303 N. Miura, T. Shidei, Y. Yuan, S. Kawai, K. Takatsu, Y. Kiyota, Y. Asano, and T. Kuroda,
"A 0.55V 10fJ/bit inductive-coupling data link and 0.7V 135fJ/cycle clock link with dual-coil transmission scheme,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 46, no. 4, pp. 965-973, Apr. 2011.
pdf
302 黒田忠広,
"ワイヤレス給電の将来展望,"
OHM, pp. 4-5, Mar. 2011.
pdf
301 T. Takeya, L. Nan, S. Nakano, N. Miura, H. Ishikuro, and T. Kuroda,
"A 12Gb/s Non-Contact Interface with Coupled Transmission lines,"
IEEE International Solid-State Circuits Conference (ISSCC'11), Dig. Tech. Papers, pp. 492-493, Feb. 2011.
pdf
300 N. Miura, Y. Take, M. Saito, Y. Yoshida, and T. Kuroda,
"A 2.7Gb/s/mm2 0.9pJ/b/Chip 1Coil/Channel ThruChip Interface with Coupled-Resonator-Based CDR for NAND Flash Memory Stacking,"
IEEE International Solid-State Circuits Conference (ISSCC'11), Dig. Tech. Papers, pp. 490-491, Feb. 2011.
pdf
299 A. Radecki, H. Chung, Y. Yoshida, N. Miura, T. Shidei, H. Ishikuro, and T. Kuroda,
"6W/25mm2 Inductive Power Transfer for Non-Contact Wafer-Level Testing,"
IEEE International Solid-State Circuits Conference (ISSCC'11), Dig. Tech. Papers, pp. 230-231, Feb. 2011.
pdf
298 T. Matsubara, I. Hayashi, A. H.Johari, S. Kumaki, K. Kohira, T. Kuroda, and H. Ishikuro,
"An 0.5V, 0.91pJ/bit, 1.1Gb/s/ch transceiver in 65nm CMOS for high-speed wireless proximity interface,"
2011 IEEE Radio & Wireless Symposium, Phoenix, Arizona, USA, Jan. 16-19, 2011.
pdf
297 Y. Take, N. Miura, and T. Kuroda,
"A 30Gb/s/link 2.2Tb/s/mm2 Inductively-Coupled Injection-Locking CDR,"
IEEE SSCS Kansai Chapter Technical Seminar, Dec. 2010.
296 Y. Chen, S. Tsukamoto, and T. Kuroda,
"A 9-bit 100-MS/s 1.46-mW Tri-Level SAR ADC in 65nm CMOS,"
IEICE Trans. Fundamentals, vol. E93-A, no. 12, Dec. 2010.
295 黒田忠広,
"近接場ワイヤレス通信が拓く3次元実装,"
NEW MEDIA, 1-2011, p. 27, Dec. 2010.
pdf
294 X. Zhu, Y. Chen, M. Kibune, Y. Tomita, T. Hamada, H. Tamura, S.
Tsukamoto, and T. Kuroda,
"A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology,"
IEICE Trans. on Fundamental of Electronics, vol.E93-A, no.12, pp. 2456-2462, Dec. 2010.
pdf
293 J. Nishimura, and T. Kuroda,
"Multiaxial Haar-Like Feature and Compact Cascaded Classifier for Versatile Recognition,"
IEEE Sensors Journal, vol. 10, no. 11, pp. 1786-1795, Nov. 2010.
pdf
292 黒田忠広,
"ワイヤレス給電,"
電子情報通信学会誌, vol. 93, no. 11, pp. 964-967, Nov. 2010.
pdf
291 I. Hayashi, T. Matsubara, S. Kumaki, A.-H. Johari, H. Ishikuro, and T. Kuroda,
"A Phase-to-Digital Convertar for Wide Tuning Range and PVT Tolerant ADPLL Operationg Down to 0.3V,"
IEEE Asian Solid-State Circuits Conference (A-SSCC'10), Proc. Tech. Papers, pp. 225-228, Nov. 2010.
pdf
290 Y. Take, N. Miura, and T. Kuroda,
"A 30Gb/s/link 2.2Tb/s/mm2 Inductively-Coupled Injection-Locking CDR,"
IEEE Asian Solid-State Circuits Conference (A-SSCC'10), Proc. Tech. Papers, pp. 81-84, Nov. 2010.
pdf
289 K. Takatsu, K. Niitsu, T. Shidei, N. Miura, and T. Kuroda,
"A 0.45V-to-2.7V Inductive-Coupling Level Shifter,"
IEEE Asian Solid-State Circuits Conference (A-SSCC'10), Proc. Tech. Papers, pp. 205-208, Nov. 2010.
pdf
288 H. Ishikuro, and T. Kuroda,
"Wireless proximity interfaces with a pulse-based inductive coupling technique,"
IEEE Communications Magazine, vol. 48, no. 10, pp. 192-199, Oct. 2010.
pdf
287 Y. Yoshida, K. Nose, Y. Nakagawa, K. Noguchi, Y. Morita, M. Tago, M. Mizuno, and T. Kuroda,
"An inductive-coupling DC voltage transceiver for highly-parallel wafer-level testing,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 45, no. 10, pp. 2057-2065, Oct. 2010.
pdf
286 K. Takatsu, H. Tamura, T. Yamamoto, Y. Doi, K. Kanda, T. Shibasaki, and T. Kuroda,
"A 60-GHz 1.65mW 25.9% Locking Range Multi-Order LC Oscillator Based Injection Locked Frequency Divider in 65nm CMOS,"
IEEE Custom Integrated Circuits Conference (CICC'10), Dig. Tech. Papers, pp. 653-656, Sep. 2010.
pdf
285 T. Takeya, K. Sunaga, K. Yamaguchi, H. Sugita, Y. Yoshida, M. Mizuno, and T. Kuroda,
"A 6Gb/s Receiver With Discrete-Time Based Channel Filtering For Wireline FDM Communications,"
IEEE Custom Integrated Circuits Conference (CICC'10), Dig. Tech. Papers, pp. 173-176, Sep. 2010.
pdf
284 M. Saito, Y. Yoshida, N. Miura, and T. Kuroda,
“47% Power Reduction and 91% Area Reduction in Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking”,
IEEE Circuits and Systems I (TCAS-I), vol. 57, Issue 9, pp. 2269–2278, Sep. 2010.
pdf
283 K. Niitsu, Y. Kohama, Y. Sugimori, K. Kasuga, K. Osada, N. Irie, H.Ishikuro, and T. Kuroda,
"Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration,"
IEEE Trans. On Very Large Scale Integration (VLSI) Systems, vol. 18, no. 8, pp. 1238-1243, Aug. 2010.
pdf
282 黒田忠広,
"2025年の半導体技術と産業と日本,"
第37回STARCアドバンスト講座 , pp. 141-149, July 2010.
281 黒田忠広,
"高性能・超低電力短距離ワイヤレス可動情報システムの創出,"
情報処理 ,vol. 51, no. 7, pp. 861-869, July 2010.
pdf
280 N. Miura, T. Shidei, Y. Yuan, S. Kawai, K. Takatsu, Y. Kiyota, Y. Asano, and T. Kuroda,
"A 0.7V 20fJ/bit Inductive-Coupling Data Link with Dual-Coil Transmission Scheme,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. 201-202, June 2010.
pdf
279 Y. Yuan, A. Radecki, N. Miura, I. Aikawa, Y. Take, H. Ishikuro, and T. Kuroda,
"Simultaneous 6Gb/s Data and 10mW Power Transmission using Nested Clover Coils for Non-Contact Memory Card,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. 199-200, June 2010.
pdf
278 Yi Zhan, J. Nishimura, and T. Kuroda,
"Human Activity Recognition from Environmental Background Sounds for Wireless Sensor Networks,"
IEEJ, vol. 130, no. 4 pp. 565-572, Apr. 2010.
277 J. Nishimura, and T. Kuroda,
"Versatile Recognition Using Haar-Like Feature and Cascaded Classifier,"
IEEE Sensors Journal, vol. 10, pp. 942-951, 2010.
pdf
276 T. Takeya, and T. Kuroda,
"MMSE Timing Recovery using Multi-Channel Early-Late Gates for Analog Multi-Tone Systems,"
4th International Symposium on Communications, Control and Signal Processing (ISCCSP'10), Mar. 2010.
pdf
275 N. Miura, K. Kasuga, M. Saito, and T. Kuroda,
"An 8Tb/s 1pJ/b 0.8mm2/Tb/s QDR Inductive-Coupling Interface Between 65nm CMOS and 0.1um DRAM,"
IEEE International Solid-State Circuits Conference (ISSCC'10), Dig. Tech. Papers, pp. 436-437, Feb. 2010.
pdf
274 M. Saito, N. Miura, and T. Kuroda,
"A 2Gb/s 1.8pJ/b/chip Inductive-Coupling Through-Chip Bus for 128-Die NAND-Flash Memory Stacking,"
IEEE International Solid-State Circuits Conference (ISSCC'10), Dig. Tech. Papers, pp. 440-441, Feb. 2010.
pdf
273 S. Kawai, H. Ishikuro, and T. Kuroda,
"A 2.5Gb/s/ch Inductive-Coupling Transceiver for Non-Contact Memory Card,"
IEEE International Solid-State Circuits Conference (ISSCC'10), Dig. Tech. Papers, pp. 264-265, Feb. 2010.
pdf
272 T. Kuroda,
"Panel Discussion: The Semiconductor Industry in 2025,"
IEEE International Solid-State Circuits Conference (ISSCC'10), Dig. Tech. Papers, Feb. 2010.
271 T. Kuroda,
"Inductively Coupled Through-Chip Interface,"
IEEE International Solid-State Circuits Conference (ISSCC'10), Dig. Tech. Papers, Feb. 2010.
270 R. Takashima, Y. Hanai, Y. Hori and T. Kuroda,
"A Versatile Recognition Processor for Sensor Network Applications,"
15th Asia and South Pacific Design Automation Conference (ASP-DAC'10), Proceedings, pp. 349-350, Jan. 2010.
pdf
269 M. Saito, Y. Sugimori, Y. Kohama, Y. Yoshida, N. Miura, H. Ishikuro, T. Sakurai, and T. Kuroda,
"2Gb/s 15pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 45, no. 1, pp. 134-141, Jan. 2010.
pdf
268 Y. Hori, Y. Hanai, J. Nishimura and T. Kuroda,
"Architecture Design of Versatile Recognition Processor for Sensornet Applications,"
IEEE Micro, vol. 29, no. 6, pp. 44-57, Nov./Dec. 2009.
pdf
267 M. Saito, K. Kasuga, T. Takeya, N. Miura, and T. Kuroda,
"An Extended XY Coil for Noise Reduction in Inductive-coupling Link,"
IEEE Asian Solid-State Circuits Conference (A-SSCC'09), Proc. Tech. Papers, pp. 305-308, Nov. 2009.
pdf
266 Y. Chen, S. Tsukamoto, and T. Kuroda,
"A 9b 100MS/s 1.46mW SAR ADC in 65nm CMOS,"
IEEE Asian Solid-State Circuits Conference (A-SSCC'09), Proc. Tech. Papers, pp. 145-148, Nov. 2009.
pdf
265 K. Kasuga, M. Saito, T. Takeya, N. Miura, H. Ishikuro and T. Kuroda,
"A Wafer Test Method of Inductive-Coupling Link,"
IEEE Asian Solid-State Circuits Conference (A-SSCC'09), Proc. Tech. Papers, pp. 301-304, Nov. 2009.
pdf
264 L. Liu, M. Takamiya, T. Sekitani, Y. Noguchi, S. Nakano, K. Zaitsu, T.Kuroda, T. Someya, and T. Sakurai,
"A 107-pJ/bit 100-kb/s 0.18-um Capacitive-Coupling Transceiver With Data Edge Signaling and DC Power-Free Pulse Detector for Printable Communication Sheet,"
IEEE Trans. On Circuits and Systems I, vol. 56, no. 11, pp. 2511-2518, Nov. 2009.
pdf
263 Y. Hanai and T. Kuroda,
"Face detection through compact classifier using adaptive look-up-table,"
IEEE International Conference on Image Processing (ICIP), pp. 1225-1228, Nov. 2009.
pdf
262 M. Sato, H. Abe, M. Hamada, H. Majima, T. Kuroda, and H. Ishikuro,
A 90nm CMOS Highly Linear Clock Bootstrapped RF Sampler Operating at Wide "Frequency Range of 0.5GHz to 5GHz,"
in Proc. 2009 IEEE Radio Frequency Integrated Circuits Symposium, Boston, MA, USA, June 7-9, 2009, pp.391-394
pdf
261 K. Niitsu, V. Kulkarni, K. Shinmo, H. Ishikuro, and T. Kuroda,
"A 14GHz AC-Coupled Clock Distribution Using Single LC-VCO and Distributed Phase Interpolatorsk,"
International Conference on Solid State Devices and Materials, pp. 82-83, Oct. 2009.
pdf
260 K.Kasuga, Y. Yuan, N. Miura, and T. Kuroda,
"Electromagnetic Interference and Susceptibility in Inductive-Coupling Link,"
JSAP Solid State Devices and Materials (SSDM), Dig. Tech. Papers, pp. 62-63, Oct. 2009.
pdf
259 T. Kuroda,
"Low-Power 3D CMOS Integration,"
JSAP Solid State Devices and Materials (SSDM) Workshop, pp. 18-26, Oct. 2009.
258 S.Saito, Y. Kohama, Y. Sugimori, Y. Hasegawa, H. Matsutani, T. Sano, K. Kasuga, Y. Yoshida, K. Niitsu, N. Miura, T. Kuroda, H. Amano,
"MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link,"
International Conference on Field Programmable Logic and Applications, pp. 6-11, Sep. 2009.
pdf
257 T. Kuroda,
"ThruChip Interface (TCI) for 3D System Integration,"
STMicroelectronics seminar, Sep. 2009.
256 M. Saito, Y. Sugimori, Y. Kohama, Y. Yoshida, N. Miura, H. Ishikuro, and T. Kuroda,
"47% Power Reduction and 91% Area Reduction in Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking,"
IEEE Custom Integrated Circuits Conference (CICC'09), Dig. Tech. Papers, pp. 449-452, Sep. 2009.
pdf
255 Y. Chen, X. Zhu, H. Tamura, M. Kibune, Y Tomita, T. Hamada, M. Yoshioka, K. Ishikawa, T. Takayama, J. Ogawa, S. Tsukamoto, and T. Kuroda,
"Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC,"
IEEE Custom Integrated Circuits Conference (CICC'09), Dig. Tech. Papers, pp. 279-282, Sep. 2009.
pdf
254 黒田忠広,
"サブpJ/bのチップ間接続を実現する誘導結合通信,"
第21回低消費電力・高速LSI技術懇談会 , Sep. 2009.
253 T. Kuroda,
"ThruChip Interface (TCI) for 3D System Integration,"
Intel seminar, Sep. 2009.
252 T. Kuroda,
"Is TSV 3D LSI’s and Packaging Finally Ready or Is It Just Another Fantasy?"
IEEE Symposium on VLSI Circuits, Joint Runmp Session, Dig. Tech. Papers, p. 173, June 2009.
251 T. Kuroda,
"Wireless TSV for Low-Power 3D System Integration,"
IEEE Symposium on VLSI Circuits, Short Course Program Digest, pp. 77-106, June 2009.
250 K. Osada, M. Saen, Y. Okuma, K. Niitsu, Y. Shimazaki, Y. Sugimori, Y. Kohama, K. Kasuga, I. Nonomura, N. Irie, T. Hattori, A. Hasegawa, and T. Kuroda,
"3D System Integration of Processor and Multi-Stacked SRAMs by Using Inductive-Coupling Links,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. 256-257, June 2009.
pdf
249 Y. Kohama, Y. Sugimori, S. Saito, Y. Hasegawa, T. Sano, K. Kasuga, Y. Yoshida, K. Niitsu, N. Miura, H. Amano, and T. Kuroda,
"A Scalable 3D Processor by Homogeneous Chip Stacking with Inductive-Coupling Link,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. 94-95, June 2009.
pdf
248 Y. Yuan, N. Miura, S. Imai, H. Ochi, and T. Kuroda,
"Digital Rosetta Stone: A Sealed Permanent Memory with Inductive-Coupling Power and Data Link,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. 26-27, June 2009.
pdf
247 S. Kawai, H. Ishikuro, and T. Kuroda,
"A 4.7 Gb/s Inductive Coupling Interposer with Dual Mode Modem,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. 92-93, June 2009.
pdf
246 黒田忠広,
"CPUとSRAMチップを誘導結合で三次元実装し,システムレベルの動作検証に成功,"
電子情報通信学会誌, vol. 92, no. 6, pp. 472-473, June 2009.
pdf
245 黒田忠広,
"無線で65チップを接続 SSDの体積を1/8へ,"
日経エレクトロニクス6月号 , pp. 77-85, June 2009.
pdf
244 黒田忠広,
"ワイヤレスTSVを用いた3次元集積,"
最先端実装技術シンポジウム , pp. 62-74, June 2009.
243 春日一貴, 新津葵一, 黒田忠広,
"誘導結合リンクを用いた90nmプロセッサと65nm SRAMの三次元システム集積,"
ICD LSIとシステムのワークショップ2009 , May 2009.
242 黒田忠広,
"科学技術・研究開発の国際比較 2009年版,"
科学技術振興機構 , pp. 12-13, May 2009.
pdf
241 黒田忠広,
"パネル・ディスカッション TSVはどこまで低コスト化し普及するのか,"
TSVテクノロジ・コンファレンス2009 , pp. 75-80, Apr. 2009.
240 黒田忠広,
"TSVを使わず無線で”コスト0”の3次元積層,"
TSVテクノロジ・コンファレンス2009 , pp. 47-74, Apr. 2009.
239 黒田忠広,
"コストがほぼゼロの無線TSV まずはメモリーで実用化を狙う,"
日経マイクロデバイス4月号 , pp. 34-37, Apr. 2009.
pdf
238 Y. Hanai, Y. Hori, J. Nishimura, and T. Kuroda,
"Architecture Design of Versatile Recognition Processor for Sensornet Applications,"
IEEE Symposium on Low-Power and High-Speed Chips COOLChips XII, Apr. 2009.
237 N. Miura, Y. Kohama, Y. Sugimori, H. Ishikuro, T. Sakurai, and T. Kuroda,
"A High-Speed Inductive-Coupling Link with Burst Transmission,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 44, no. 3, pp. 947-955, Mar. 2009.
pdf
236 Y. Yoshida, K. Nose, Y. Nakagawa, K. Noguchi, Y. Morita, M. Tago, T. Kuroda, and M. Mizuno,
"Wireless DC Voltage Transmission Using Inductive-Coupling Channel for Highly-Parallel Wafer-Level Testing,"
Highlights of ISSCC 2009 - Beijing, China, Mar. 2009.
235 吉田洋一, 野瀬浩一, 中川源洋, 野口宏一郎, 森田泰弘, 田子雅基, 黒田忠広, 水野正之,
"Wireless DC Voltage Transmission Using Inductive-Coupling Channel for Highly-Parallel Wafer-Level Testing,"
ISSCC 2009 報告会 , Mar. 2009.
234 V. Kulkarni, M. Muqsith, K. Niitsu, H. Ishikuro, and T. Kuroda,
"A 750 Mb/s, 12 pJ/b, 6-to-10 GHz CMOS IR-UWB transmitter with embedded on-chip antenna,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 44, no. 2, pp. 394-403, Feb. 2009.
pdf
233 Y. Hanai, Y. Hori, J. Nishimura, and T. Kuroda,
"A Versatile Recognition Processor Employing Haar-Like Feature and Cascaded Classifier,"
IEEE International Solid-State Circuits Conference (ISSCC'09), Dig. Tech. Papers, pp. 148-149, Feb. 2009.
pdf
232 K. Niitsu, Y. Shimazaki, Y. Sugimori, Y. Kohama, K. Kasuga, I. Nonomura, M. Saen, S. Komatsu, K. Osada, N. Irie, T. Hattori, A. Hasegawa, and T. Kuroda,
"An Inductive-Coupling Link for 3D Integration of a 90nm CMOS Processor and a 65nm CMOS SRAM,"
IEEE International Solid-State Circuits Conference (ISSCC'09), Dig. Tech. Papers, pp. 480-481, Feb. 2009.
pdf
231 Y. Sugimori, Y. Kohama, M. Saito, Y. Yoshida, N. Miura, H. Ishikuro, T. Sakurai, and T. Kuroda,
"A 2Gb/s 15pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking,"
IEEE International Solid-State Circuits Conference (ISSCC'09), Dig. Tech. Papers, pp. 244-245, Feb. 2009.
pdf
230 Y. Yoshida, K. Nose, Y. Nakagawa, K. Noguchi, Y. Morita, M. Tago, T. Kuroda, and M. Mizuno,
“Wireless DC Voltage Transmission Using Inductive-Coupling Channel for Highly-Parallel Wafer-Level Testing,”
IEEE International Solid-State Circuits Conference (ISSCC'09), Dig. Tech. Papers, pp. 470-471, Feb. 2009.
pdf
229 J. Nishimura and T. Kuroda,
"Speaker recognition using speaker-independent universal acoustic model and synchronous sensing for Business Microscope,"
International Symposium on Wireless Pervasive Computing (ISWPC), Feb. 2009.
pdf
228 S. Kawai, T. Ikari, Y. Takikawa, H. Ishikuro, and T. Kuroda,
"A Wireless Real-Time On-chip Bus Trace System,"
in 14th Asia and South Pacific Design Automation Conference (ASP-DAC'09), Jan. 2009.
pdf
227 X. Zhu, S. Tsukamoto, and T. Kuroda,
"A 1 GHz CMOS Comparator with Dynamic Offset Control Technique,"
in 14th Asia and South Pacific Design Automation Conference (ASP-DAC'09), Jan. 2009.
pdf
226 Y. Hanai, J. Nishimura, and T. Kuroda,
"HAAR-LIKE FILTERING FOR HUMAN ACTIVITY RECOGNITION USING 3D ACCELEROMETER,"
IEEE 13th Digital Signal Processing and 5th Signal Processing Education workshop, pp. 675-678, Jan. 2009.
pdf
225 J. Nishimura and T. Kuroda,
"HAAR-LIKE FILTERING WITH CENTER-CLIPPED EMPHASIS FOR SPEECH DETECTION IN SENSORNET,"
IEEE 13th Digital Signal Processing and 5th Signal Processing Education workshop, pp. 1-4, Jan. 2009.
pdf
224 J. Nishimura, N. Sato, and T. Kuroda,
"Speaker Siglet Detection for Business Microscope,"
AMLA/IEEE 7th Interrnational Conference on Machine Learning and Applications (ICMLA), pp. 376-381, Dec. 2008.
pdf
223 J.Nishimura and T. Kuroda,
"Haar-like Filtering Based Speech Detection using Integral Signalsfor Sensornet,"
International Conference on Sensing Technology (ICST08), Proceedings, pp. 52-56, Dec. 2008.
pdf
222 S. Kawai,  T. Ikari, Y. Takikawa, H. Ishikuro, and T. Kuroda, 
"A Wireless Real-Time On-Chip Bus Trace System Using Quasi-Synchronous Parallel Inductive Coupling Transceivers," IEEE Asian Solid-State Circuits Conference (A-SSCC'08), Proc. Tech. Papers, pp. 113-116, Dec. 2008.
pdf
221 K. Niitsu, S. Kawai,  N. Miura, H. Ishikuro, and T. Kuroda, "A 65fJ/b Inductive-Coupling Inter-Chip Transceiver Using Charge Recycling Technique for Power-Aware 3D System Integration,"
IEEE Asian Solid-State Circuits Conference (A-SSCC'08), Proc. Tech. Papers, pp. 97-100, Nov. 2008.
pdf
220 Y. Yoshida, N. Miura, and T. Kuroda,
"A 2 Gb/s bi-directional inter-chip data transceiver with differential inductors for high density inductive channel array,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 43, no.11, pp. 2363-2369, Nov. 2008.
pdf
219 J. Nishimura and T. Kuroda, "Low Cost Speech Detection using Haar-like Filtering for Sensornet," The 9th International Conference on Signal Processing (ICSP08), Proceedings, vol. 3, pp. 2608-2611, Oct. 2008. pdf
218 X. Zhu, Y. Chen, M. Kibune, Y. Tomita, T. Hamada, H. Tamura, S. Tsukamoto, and T. Kuroda,
"A dynamic offset control technique for comparator design in scaled CMOS technology,"
IEEE Custom Integrated Circuits Conference (CICC'08), Dig. Tech. Papers, pp. 495-498, Sep. 2008.
pdf
217 中川源洋, 吉田洋一, 野瀬浩一, 黒田忠広, 水野正之,
"誘導結合チップ間リンクの通信距離拡張技術,"
2008 IEICEソサイエティ大会 , Sep. 2008.
216 K. Niitsu, Y. Kohama, Y. Sugimori, K. Osada, N. Irie, H. Ishikuro, and T. Kuroda,
"Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for 3D System Integration,"
International Conference on Solid-State Devices and Materials, pp. 86-87, Sep. 2008.
pdf
215 K. Niitsu, Y. Yuxiang, H. Ishikuro, and T. Kuroda,
"A 33% Improvement in Efficiency of Wireless Inter-Chip Power Delivery by Thin Film Magnetic Material,"
International Conference on Solid-State Devices and Materials, pp. 492-493, Sep. 2008.
pdf
214 V. Kulkarni and T. Kuroda,
"A 750Mb/s 12pJ/b 6-to-10GHz Digital UWB Transmitter,"
2008 KAIST-Keio-Tsinghua International Workshop on SoC, Sep. 2008.
213 K. Niitsu and T. Kuroda,
"Experimental Verification of Interference from Power/Signal Lines and to SRAM Circuits in Inductive-Coupling Inter-Chip Link,"
2008 KAIST-Keio-Tsinghua International Workshop on SoC, Sep. 2008.
212 N. Miura and T. Kuroda,
"A High-Speed Inductive-Coupling Link with Burst Transmission,"
2008 KAIST-Keio-Tsinghua International Workshop on SoC, Sep. 2008.
211 J. Nishimura and T. Kuroda,
"Speech Detection using Haar-like Filtering for Sensornet,"
2008 KAIST-Keio-Tsinghua International Workshop on SoC, Sep. 2008.
210 三浦典之, 黒田忠広,
"3次元実装のための低電力・広帯域誘導結合通信,"
エレクトロニクス実装学会誌 , vol. 11, no. 3, pp. 174-181, May 2008.
pdf
209 T. Kuroda,
"CMOS Proximity Inter-Chip Communications (Plenary Talk),"
The 5th International Workshop on Nanoscale Semiconductor Devices, Proceedings, pp. 3-45, May 2008.
208 J. Nishimura and T. Kuroda,
"Eating habits monitoring using wireless wearable in-ear microphone,"
International Symposium on Wireless Pervasive Computing (ISWPC08), pp. 130-133, May 2008.
pdf
207 Y. Yuxiang, Y. Yoshida, N. Yamagish, and T. Kuroda,
"Chip-to-Chip Power Delivery by Inductive Coupling with Ripple Canceling Scheme,"
Japanese Journal of Applied Physics (JJAP), vol. 47, no.4, Apr. 2008.
pdf
206 J. Nishimura, N. Sato, and T. Kuroda,
"Speech Siglet Detection For Business Microscope,"
IEEE International Conference on Pervasive Computing and Communications (PerCom), pp. 147-152, Mar. 2008.
pdf
205 T. Shibasaki, H. Tamura, K. Kanda, H. Yamaguchi, J. Ogawa, and T. Kuroda,
"20-GHz quadrature injection-locked LC dividers with enhanced locking range,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 43, no. 3, pp. 610-618, Mar. 2008.
pdf
204 D. Mizoguchi, N. Miura, H. Ishikuro, and T. Kuroda,
"Constant Magnetic Field Scaling in Inductive-Coupling Data Link,"
IEICE Transactions on Electronics, Vol. E91-C, No. 2, pp. 200- 205, Feb. 2008.
pdf
203 L. Lechang, M. Takamiya, T. Sekitani, Y. Noguchi, S. Nakano,
K. Zaitsu, T. Kuroda, T. Someya, and T. Sakurai,
"A 107pJ/b 100kb/s 0.18um Capacitive-Coupling Transceiver for Printable Communication Sheet,"
IEEE International Solid-State Circuits Conference (ISSCC'08), Dig. Tech. Papers,
pp. 292-614, Feb. 2008.
202 N. Miura, Y. Kohama, Y. Sugimori, H. Ishikuro, T. Sakurai, and T. Kuroda,
"An 11Gb/s Inductive-Coupling Link with Burst Transmission,"
IEEE International Solid-State Circuits Conference (ISSCC'08), Dig. Tech. Papers, pp. 298-299, Feb. 2008.
pdf
201 黒田忠広,
"科学技術・研究開発の国際比較 2008年版,"
科学技術振興機構 , p. 8, p. 22, Feb. 2008.
pdf
200 Y. Yuxiang, Y. Yoshida, and T. Kuroda,
"Non-Contact 10% Efficient 36mW Power Delivery Using On-Chip Inductor in 0.18-um CMOS,"
電子情報通信学会集積回路研究会 , Jan. 2008.
199 N. Miura, H. Ishikuro, K. Niitsu, T. Sakurai, and T. Kuroda,
"A 0.14pJ/b inductive-coupling transceiver with digitally-controlled precise pulse shaping,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 43, no. 1, pp. 285-291, Jan. 2008.
pdf
198 T. Kuroda,
"Wireless Proximity Communications for 3D System Integration,"
IEEE International Workshop on Radio-Frequency Integration Technology (RFIT'07), pp. 21-25, Dec. 2007.
pdf
197 N. Nedovic, N. Tzartzanis, H. Tamura, F.M. Rotella, M. Wiklund, Y. Mizutani, Y. Okaniwa, T. Kuroda, J. Ogawa, and W.W. Walker,
"A 40-44 Gb/s 3× oversampling CMOS CDR/1:16 DEMUX,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 42, no. 12, pp. 2726-2735, Dec. 2007.
pdf
196 H. Ishikuro, N. Miura, and T. Kuroda,
"Wideband Inductive-coupling Interface for High-performance Portable System,"
IEEE Custom Integrated Circuits Conference (CICC'07), Dig. Tech. Papers, pp. 13-20, Sep. 2007.
pdf
195 N. Miura and T. Kuroda,
"Inductive-Coupling Transceiver for 3D System Integrarion,"
Proc. 2007 International Conference on Integrated Circuit Design and Technology (ICICDT),
pp. 1-4, May 2007.
pdf
194 黒田忠広,
"システムLSIの低電力技術,"
電子情報通信学会誌, vol. 90, no. 11, pp. 977-981, Nov. 2007.
pdf
193 吉田洋一, 三浦典之, 黒田忠広,
“2Gb/s 双方向送受信器を用いた三次元積層チップ間誘導結合インタフェースの高密度化,”
第11回システムLSIワークショップ, Nov. 2007.
192 K. Niitsu, Y. Sugimori, Y. Kohama, K. Osada, N. Irie, H. Ishikuro, and T. Kuroda,
“Interference from Power/Signal Lines and to SRAM Circuits in
65nm CMOS Inductive-Coupling Link,”
IEEE Asian Solid-State Circuits Conference (A-SSCC'07), Proc. Tech. Papers, pp. 131-134, Nov. 2007.
pdf
191 Y. Yoshida, N. Miura, and T. Kuroda,
“A 2Gb/s Bi-Directional Inter-Chip Data Transceiver with
Differential Inductors for High Density Inductive Channel Array,”
IEEE Asian Solid-State Circuits Conference (A-SSCC'07), Proc. Tech. Papers, pp. 127-130, Nov. 2007.
pdf
190 Y. Yuxiang, Y. Yoshida, and T. Kuroda,
“Non-Contact 10% Efficient 36mW Power Delivery Using On-Chip Inductor in 0.18-um CMOS,”
IEEE Asian Solid-State Circuits Conference (A-SSCC'07), Proc. Tech. Papers, pp. 115-118, Nov. 2007.
pdf
189 A. Kumar, N. Miura, and T. Kuroda,
“Capacitor-Shunted Transmitter for Power Reduction in Inductive-Coupling Clock Link,”
Solid State Devices and Materials (SSDM'07), Extended Abstracts, pp. 1068-1069, Sep. 2007.
pdf
188 Y. Yuxiang, Y. Yoshida, N. Yamagishi, and T. Kuroda,
“Chip-to-Chip Power Delivery by Inductive Coupling with Ripple Cancelling Scheme,”
Solid State Devices and Materials (SSDM'07), Extended Abstracts, pp. 502-503, Sep. 2007.
pdf
187 V. Kulkarni, M. Muqsith, H. Ishikuro, and T. Kuroda,
"A 750Mb/s 12pJ/b 6-to-10GHz Digital UWB Transmitter,"
IEEE Custom Integrated Circuits Conference (CICC'07), Dig. Tech. Papers, pp. 647-650, Sep. 2007.
pdf
186 T. Shibasaki and T. Kuroda,
"A 20-GHz Injection-Locked LC Divider with a 25-% Locking Range,"
2007 KAIST-Keio-Tsinghua International Workshop on SoC, June 2007.
185 N. Yamagishi, Y. Hori, and T. Kuroda,
"A 0.79mm2 29mW Real-Time Face Detection IP Core,"
2007 KAIST-Keio-Tsinghua International Workshop on SoC, June 2007.
184 H. Ishikuro,
"An Attachable Wireless Chip Access Interface Using Pulse-Based Inductive-Coupling through
LSI Package,"
2007 KAIST-Keio-Tsinghua International Workshop on SoC, June 2007.
183 Y. Shimazaki,
"Low Power Techniques for Mobile Processors,"
2007 KAIST-Keio-Tsinghua International Workshop on SoC, June 2007.
182 N. Miura and T. Kuroda,
"Inductive-Coupling Transceiver for 3D Chipstacks,"
2007 KAIST-Keio-Tsinghua International Workshop on SoC, June 2007.
181 吉田洋一, 黒田忠広,
"90nm CMOS 誘導結合トランシーバ,"
VDEC ASPLA応募スキーム報告会, May 2007.
180 Y. Hori and T. Kuroda,
"A 0.79-mm2 29-mW real-time face detection core,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 42, no.3, pp. 790-797, Apr. 2007.
pdf
179 三浦典之, 石黒仁揮, 桜井貴康, 黒田忠広,
"0.14pJ/b 誘導結合トランシーバ,"
電子情報通信学会技術研究報告, vol. 107, no. 1, pp. 65-69, Apr. 2007.
178 K. Niitsu, N. Miura, M. Inoue, Y. Nakagawa, M. Tago, M. Mizuno, H. Ishikuro, and T. Kuroda,
"60% Power Reduction in Inductive-Coupling Inter-Chip Link by Current-Sensing Technique,"
Japanese Journal of Applied Physics, vol. 46, no. 4B, pp. 2215-2219, Apr. 2007.
pdf
177 Y. Zhan, S. Miura, J. Nishimura, and T. Kuroda,
"Human Activity Recognition from Environmental Background Sounds for Wireless Sensor Networks,"
IEEE International Conference on Networking, Sensing and Control (ICNSC2007),
pp. 307-312, Apr. 2007.
pdf
176 T. Shibasaki, H. Tamura, K. Kanda, H. Yamaguchi, J. Ogawa, and T. Kuroda,
"18-GHz Clock Distribution Using a Coupled VCO Array,"
IEICE Trans. Electron, vol. E90-C, no. 4, pp. 811-822, Apr. 2007.
pdf
175 K. Niitsu, N. Miura, M. Inoue, Y. Nakagawa, M. Tago, M. Mizuno, T. Sakurai, and T. Kuroda,
"Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link,"
IEICE Trans. Electron, vol. E90-C, no. 4, pp. 829-835, Apr. 2007.
pdf
174 Y. Tomita, H. Tamura, M. Kibune, J. Ogawa, K. Gotoh, and T. Kuroda,
"A 20-Gb/s simultaneous bidirectional transceiver using a resistor-transconductor hybrid in 0.11-µm CMOS,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 42, no. 4, pp. 627-636, Mar. 2007.
pdf
173 黒田忠広,
"超低電力短距離ワイヤレス可動情報システム,"
電子情報通信学会誌, vol. 90, no. 3, pp. 191-195, Mar. 2007.
pdf
172 N. Nedovic, N. Tzartzanis, H. Tamura, F. Rotella, M. Wiklund, Y. Mizutani, Y. Okaniwa, T. Kuroda, J. Ogawa, W. Walker,
"A 40-to-44Gb/s 3x— Oversampling CMOS CDR/1:16 DEMUX,"
IEEE International Solid-State Circuits Conference (ISSCC'07), Dig. Tech. Papers,
pp. 224-225, Feb. 2007.
pdf
171 N. Miura, H. Ishikuro, T. Sakurai, and T. Kuroda,
"A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with
Digitally-Controlled Precise Pulse Shaping,"
IEEE International Solid-State Circuits Conference (ISSCC'07), Dig. Tech. Papers,
pp. 264-265, Feb. 2007.
pdf
170 H. Ishikuro, T. Sugahara, and T. Kuroda,
"An Attachable Wireless Chip Access Interface for Arbitrary Data Rate by Using Pulse-Based Inductive-Coupling through LSI Package,"
IEEE International Solid-State Circuits Conference (ISSCC'07), Dig. Tech. Papers,
pp. 360-361,608, Feb. 2007.
pdf
169 N. Miura, T. Sakurai, and T. Kuroda,
"Crosstalk countermeasures for high-density inductive-coupling channel array,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 42, no. 2, pp. 410-421, Feb. 2007.
pdf
168 N. Miura, D. Mizoguchi, M. Inoue, K. Niitsu, Y. Nakagawa, M. Tago, M. Fukaishi, T. Sakurai, and T. Kuroda,
"A 1Tb/s 3W inductive-coupling transceiver for 3D-stacked inter-chip clock and data link,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 42, no. 1, pp. 111-122, Jan. 2007.
pdf
167 N. Miura and T. Kuroda,
"A 1Tb/s 3W Inductive-Coupling Transceiver Chip,"
12th Asia and South Pacific Design Automation Conference (ASP-DAC'07), pp. 92-93, Jan. 2007.
166 D. Mizoguchi, N. Miura, H. Ishikuro, and T. Kuroda,
"Constant Magnetic Field Scaling in Inductive-Coupling Data Link,"
International Conference on Solid State Devices and Materials (SSDM'06), pp. 606-607, Sep. 2006.
165 K. Onizuka, H. Kawaguchi, M. Takamiya,T. Kuroda, and T. Sakurai,
"Chip-to-Chip Inductive Wireless Power Transmission System for SiP Applications,"
in Proc. IEEE Custom Integrated Circuits Conference (CICC’06), pp. 575-578, May 2006.
pdf
164 黒田忠広, 井上眞梨,
"研究成果が社会に浸透する姿を目の当たりにできる最先端技術の世界"
河合塾、栄冠めざしてSPECIAL特集号, p. 81, 2006.
pdf
163 T. Kuroda,
"Future Digital Link,"
IEEE Asian Solid-State Circuits Conference (A-SSCC'06), p. 454, Oct. 2006.
162 黒田忠広,
"2006 IEEE Symposium on VLSI Circuits報告,"
低消費電力・高速LSI技術懇談会, Sep. 2006.
161 三浦典之,
"慶應黒田研VDEC試作チップデザインレビュー:三次元積層チップ間誘導結合トランシーバ,"
VDECデザイナーフォーラム, Sep. 2006.
160 三浦典之, 黒田忠広,
"90nm CMOS 誘導結合トランシーバ,"
VDEC ASPLA応募スキーム報告会, Sep. 2006.
159 T. Kuroda and N. Miura,
"Perspective of Low-Power and High-Speed Wireless Inter-Chip Communications for
SiP Integration (Plenary),"
2006 European Solid-State Circuits Conference (ESSCIRC'06), Dig. Tech. Papers,
pp. 3-6, Sep. 2006.
pdf
158 N. Miura, Y. Nakagawa, M. Tago, M. Fukaishi,
T. Sakurai, and T. Kuroda,
"A 1Tb/s 3W Inductive-Coupling Transceiver for 3D ICs,"
2006 Intenational PhD Workshop on SoC (IPS), July 2006.
157 Y. Hori, M. Kusaka, and T. Kuroda,
"A 0.79mm2 29mW Real-Time Face Detection Core,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. 188-189, June 2006.
pdf
156 T. Shibasaki, H. Tamura, K. Kanda, H. Yamaguchi, J. Ogawa, and T. Kuroda,
"A 20-GHz Injection-Locked LC Divider with a 25-% Locking Range,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. 212-213, June 2006.
pdf
155 M. Inoue, N. Miura, K. Niitsu, Y. Nakagawa, M. Tago, M. Fukaishi, T. Sakurai, and T. Kuroda,
"Daisy Chain for Power Reduction in Inductive-Coupling CMOS Link,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. 80-81, June 2006.
pdf
154 富田安基, 田村泰孝, 木船雅也, 小川淳二, 後藤公太郎, 黒田忠広,
"Resister-Transconductorハイブリッド回路を用いた20Gb/s同時双方向送受信回路,"
電子情報通信学会技報 vol. 106, no. 71, ICD2006-39, pp. 101-104, May 2006.
pdf
153 三浦典之, 溝口大介, 井上眞梨, 新津 葵一, 中川源洋, 田子雅基, 深石宗生, 桜井貴康, 黒田忠広,
"1Tb/s 3W チップ間誘導結合クロックデータトランシーバ,"
電子情報通信学会技報 vol.106, no.71, ICD2006-22~39, pp. 95-100, May 2006.
pdf
152 黒田忠広,
"夢を形に、世界へ発信。"
SEAJ Journal 2006. 5 No. 102, pp. 35-37, May 2006.
pdf
151 三浦典之, 黒田忠広,
"1Tb/s 3W 三次元積層チップ間誘導結合インタフェース,"
第8回LSI IPデザインアワード, May 2006.
pdf
150 D. Mizoguchi, N. Miura, Y. Yoshida, N. Yamagishi, and T. Kuroda,
"Measurement of Inductive Coupling in Wireless Superconnect,"
Japanese Journal of Applied Physics (JJAP), vol. 45, no. 4B, pp. 3286-3289, Apr. 2006.
149 T. Terada, S. Yoshizumi, M. Muqsith, Y. Sanada, and T. Kuroda,
"A CMOS ultra-wideband impulse radio transceiver for 1-Mb/s data communications and 2.5-cm range finding,"
IEEE Journal of Solid-State Circuits (JSSC), pp. 891-898, Apr. 2006.
pdf
148 黒田忠広,
"パネル討論: Lifestyle Revolution Brought by Emerging Technology,"
NECテクノロジーフォーラム, Apr. 2006.
147 黒田忠広,
"チップ間を1Tビット/秒で伝送できる無線通信技術を開発 磁界結合を利用,"
Nikkei Electronics, pp. 137-148, Mar. 2006.
pdf
146 黒田忠広,
"LSI回路設計技術,"
電子情報通信学会誌, vol. 89, no. 2, pp. 96-101, Feb. 2006.
pdf
145 N. Miura, D. Mizoguchi, M. Inoue, K. Niitsu, Y. Nakagawa, M. Tago,
M. Fukaishi, T. Sakurai, and T. Kuroda,
"A 1Tb/s 3W Inductive-Coupling Transceiver for Inter-Chip Clock and Data Link,"
IEEE International Solid-State Circuits Conference (ISSCC'06), Dig. Tech. Papers,
pp. 424-425, Feb. 2006.
pdf
144 Y. Tomita, H. Tamura, M. Kibune, J. Ogawa, K. Gotoh, and T. Kuroda,
"A 20Gb/s Bidirectional Transceiver Using a Resistor-Transconductor Hybrid,"
IEEE International Solid-State Circuits Conference (ISSCC'06), Dig. Tech. Papers,
pp. 518-519, Feb. 2006.
pdf
143 N. Miura, D. Mizoguchi, M. Inoue, T. Sakurai, and T. Kuroda,
"A 195-Gb/s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a package,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 41, no. 1, pp. 23-34, Jan. 2006.
pdf
142 A. Kumar, N. Miura, M. Muqsith, and T. Kuroda,
"Active Crosstalk Cancel for High-Density Inductive Inter-Chip Wireless Communication,"
International Conference on VLSI Design, pp. 137-148, Jan. 2006.
pdf
141 T. Kuroda,
"System LSI: Challenges and Opportunities (Keynote),"
4th EU-Japan Joint Symposium on Plasma Processes, Jan. 2006.
140 S. Miura, Y. Zhan, and T. Kuroda,
"Evaluation of Parking Search using Sensor Network,"
IEEE International Symposium on Wireless Pervasive Computing 2006, Jan. 2006.
pdf
139 三浦典之, 黒田忠広,
"195Gb/s 1.2W 三次元積層チップ間誘導結合インタフェース,"
第9回システムLSIワークショップ, Nov. 2005.
pdf
138 "Si貫通 チップの構造革命,"
Nikkei Electronics, pp. 82-99, Oct. 2005.
pdf
137 T. Kuroda,
"Power Reduction in High-Speed Inter-Chip Data Communications,"
IEEE 6th International Conference on ASIC (ASICON 2005), pp. 3-7, Oct. 2005.
pdf
136 黒田忠広,
"2005 IEEE Symposium on VLSI Circuits Report,"
Electronic Journal, pp. 78-79, Oct. 2005.
pdf
135 D. Mizoguchi, N. Miura, Y. Yoshida, N. Yamagishi, and T. Kuroda,
"Measurement of Inductive Coupling in Wireless Superconnect,"
International Conference on Solid State Devices and Materials (SSDM'05), pp. 670-671, Sep. 2005.
pdf
134 黒田忠広, 眞田幸俊,
"ユビキタス・コンピューティングのための低コストで低電力な短距離ワイヤレス接続技術,"
STARC技術移転セミナー, Sep. 2005.
133 黒田忠広,
"ユビキタス・コンピューティングのための低コストで低電力な短距離ワイヤレス接続技術,"
STARCワークショップ, Sep. 2005.
132 T. Kuroda,
"Power-aware Data Communications,"
FLA Special Seminar, Sep. 2005.
131 T. Kuroda,
"System LSI: Challenges and Opportunities,"
COE 4th Hiroshima International Workshop, pp. 11-21, Sep. 2005.
130 Y. Okaniwa, H. Tamura, M. Kibune, D. Yamazaki, T. S. Cheung, J. Ogawa,
N. Tzartzanis, W. W. Walker, and T. Kuroda,
"A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 40, no. 8, pp. 1680-1687, Aug. 2005.
pdf
129 M. Muqsith and T. Kuroda,
"A CMOS Impulse Radio Ultra-Wideband Transceiver for 1Mb/s Data Communications and
±2.5cm Range Findings,"
The 2nd KAIST-KEIO-TSINGHUA University VLSI Design & SoC Workshop, Aug. 2005.
128 H. Tsuji and T. Kuroda,
"A Study on a Hybrid Architecture A/D Converter,"
The 2nd KAIST-KEIO-TSINGHUA University VLSI Design & SoC Workshop, Aug. 2005.
127 S. Miura and T. Kuroda,
"A Study on Parking Search using Wireless Sensor Network,"
The 2nd KAIST-KEIO-TSINGHUA University VLSI Design & SoC Workshop, Aug. 2005.
126 M. Kusaka and T. Kuroda,
"A Study on Real-time Face Detection LSI Using Genetic Algorithm,"
The 2nd KAIST-KEIO-TSINGHUA University VLSI Design & SoC Workshop, Aug. 2005.
125 N. Miura and T. Kuroda,
"A 195Gb/s 1.2W 3D-Stacked Inductive Inter-Chip Wireless Superconnect with
Transmit Power Control Scheme,"
The 2nd KAIST-KEIO-TSINGHUA University VLSI Design & SoC Workshop, Aug. 2005.
124 Y. Tomita and T. Kuroda,
"A 10Gb/s Receiver with Series Equalizer and On-chip ISI Monitor in 0.11um CMOS,"
The 2nd KAIST-KEIO-TSINGHUA University VLSI Design & SoC Workshop, Aug. 2005.
123 黒田忠広,
"2005 VLSI 回路シンポジウム報告,"
「応用物理」第74巻第9号(2005年9月号)ぶらっくぼーど欄, p. 1249, Sep. 2005.
122 黒田忠広,
"2005 VLSI サーキットシンポジウム報告,"
工業調査会『電子材料』, pp. 74-75, Sep. 2005.
121 黒田忠広,
"2005 IEEE Symposium on VLSI Circuits Report,"
Electronic Journal, pp. 62-63, July 2005.
pdf
120 T. Terada, S. Yoshizumi, Y. Sanada, and T. Kuroda,
"A CMOS Impulse Radio Ultra-Wideband Transceiver for
1Mb/s Data Communications and ±2.5cm Range Findings,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. 30-33, June 2005.
pdf
119 三浦典之, 溝口大介, 井上眞梨, 桜井貴康, 黒田忠広,
"195Gb/s 1.2W 電力制御機能付き3次元積層型誘導結合無線超配線,"
電子情報通信学会技報 vol. 105, no. 96, ICD2005-28~39, pp. 45-50, May 2005.
pdf
118 D. Mizoguchi, N. Miura, M. Inoue, and T. Kuroda,
"Design of Transceiver Circuits for NRZ Signaling in Inductive Inter-chip Wireless Superconnect,"
2005 International Conference on Integrated Circuit Design and Technology (ICICDT),
pp. 59-62, May 2005.
pdf
117 Y. Tomita, M. Kibune, J. Ogawa, W. Walker, H. Tamura, and T. Kuroda,
"A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-um CMOS,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 40, no. 40, pp. 986-993, Apr. 2005.
pdf
116 N. Miura, D. Mizoguchi, T. Sakurai, and T. Kuroda,
"Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect,"
IEEE Journal of Solid-State Circuits (JSSC), vol.40, no.4, pp. 829-837, Apr. 2005.
pdf
115 黒田忠広,
"DRAM混載に匹敵する伝送速度を無線のチップ間接続で達成,"
Nikkei Microdevices, pp. 74-75, Mar. 2005.
pdf
114 N. Miura, D. Mizoguchi, M. Inoue, H. Tsuji, T. Sakurai, and T. Kuroda,
"A 195Gb/s 1.2W 3D-Stacked Inductive Inter-Chip Wireless Superconnect with Transmit Power Control Scheme,"
IEEE International Solid-State Circuits Conference (ISSCC'05), Dig. Tech. Papers, pp. 264-265, Feb. 2005.
pdf
113

黒田忠広,
"インターネットゼロ(監修),"
日経サイエンス2005年1月号, Dec. 2004.

112 T. Kuroda,
"CICC 2004 Report,"
Electronic Journal, pp. 118-119, Nov. 2004.
pdf
111 古川潤, 眞田幸俊, 黒田忠広,
"マルチパス通信路におけるIR-UWBの高速同期捕捉方法の提案,"
電子情報通信学会 ワイドバンドシステム研究会 (WBS), Oct. 2004.
110 N. Miura, D. Mizoguchi, T. Sakurai, and T. Kuroda,
"Cross Talk Countermeasures in Inductive Inter-Chip Wireless Superconnect,"
in Proc. IEEE Custom Integrated Circuits Conference (CICC'04), pp. 99-102, Oct. 2004.
pdf
109 J. Furukawa, Y. Sanada, and T. Kuroda,
"Novel Initial Acquisition Scheme for IR-UWB Systems in Multipath Channel,"
in Proc. the Seventh International Symposium on Wireless Personal Multimedia Communications, Vol.1, pp. 45-49, Sep. 2004.
108 Y. Hori and T. Kuroda,
"A Study on Real-Time Face Detection LSI Using Genetic Algorithm as an Application of Wireless Interconnect Technologies for LSI Chip,"
Internatinal Workshop on Optical and Electronic Device Technology for Access Network,
Sep. 2004.
107 Y. Okaniwa and T. Kuroda,
"A Study on a 40-Gb/s Clocked Comparator in CMOS Technology for Chip-to-chip Interconnect Technology,"
Internatinal Workshop on Optical and Electronic Device Technology for Access Network, Sep. 2004.
pdf
106 Y. Tomita and T. Kuroda,
"CMOS Equalizer and ISI Monitor for High-Speed Data Communication,"
Internatinal Workshop on Optical and Electronic Device Technology for Access Network, Sep. 2004.
pdf
105 T. Kuroda,
"Wireless Super-Connect for System-in-a-Package,"
COE International Workshop, Sep. 2004.
104 黒田忠広,
"ユビキタス社会に向けた低電力CMOS設計,"
「応用物理」第73巻第9号(2004年9月号), pp. 1184-1187, Sep. 2004.
pdf
103 黒田忠広,
"2004 Simposium on VLSI Circuits報告,"
「応用物理」第73巻第9号(2004年9月号)ぶらっくぼーど欄, Sep. 2004.
102 黒田忠広,
"ユビキタスコンピューティングのための近距離データ通信技術,"
STARCシンポジウム, pp. 91-123, Sep. 2004.
101 黒田忠広,
"2004 VLSI サーキットシンポジウム報告,"
工業調査会『電子材料』, pp. 76-77, Sep. 2004.
100 黒田忠広,
"ユビキタス社会実現のための次世代無線技術の最新動向-UWBを中心に,"
DAFS技術セミナー応用編, Sep. 2004.
99 三浦典之, 溝口大介, ユスミラズ・ビンティ・ユスフ, 桜井貴康, 黒田忠広,
"誘導結合チップ間無線超配線用インダクタおよび送受信回路の解析と設計,"
電子情報通信学会技報, vol.104, no.248, SDM2004-120~139, pp. 73-78, Aug. 2004.
pdf
98 Y. Hori, K. Shimizu, Y. Nakamura, and T. Kuroda,
"A Real-Time Multi Face Detection Technique Using Positive-Negative Lines-of-Face Template,"
International Conference on Pattern Recognition, vol. 1, no. 7, Aug. 2004.
pdf
97 黒田忠広,
"2004 Symposium onVLSI Circuitsレポート,"
Electronic Journal 7月号, pp. 74-75, July 2004.
pdf
96 黒田忠広,
"UWB対応の低消費電力LSI設計技術,"
Electronic Journal 82th Technical Symposium, pp. 79-98, June 2004.
95 Y. Tomita, M. Kibune, J. Ogawa, W. Walker, H. Tamura, and T. Kuroda,
"A 10Gb/s Receiver with Equalizer and On-chip ISI Monitor in 0.11µm CMOS,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. 202-205, June 2004.
pdf
94 Y. Okaniwa, H. Tamura, M. Kibune, D. Yamazaki, T. Cheung, J. Ogawa, N. Tzartzanis, W. Walker, and T. Kuroda,
"A 0.11µm CMOS Clocked Comparator for High-Speed Serial Communications,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. 198-201, June 2004.
pdf
93 N. Miura, D. Mizoguchi, Y. Yusof, T. Sakurai, and T. Kuroda,
"Analysis and Design of Transceiver Circuit and Inductor Layout for Inductive Inter-chip Wireless Superconnect,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. 246-249, June 2004.
pdf
92

古川潤, 眞田幸俊, 黒田忠広,
"インパルスベースのUWBにおける新しい同期捕捉方法の提案,"
電子情報通信学会総合大会, A-5-43, May 2004.

91 古川潤, 眞田幸俊, 黒田忠広,
"IR-UWBにおける新しい同期補足方法の提案,"
電子情報通信学会技術報告, WBS2003-168, May 2004.
90 J. Furukawa, Y. Sanada, and T. Kuroda,
"Novel Initial Acquisition Scheme for Impulse Based UWB Systems,"
in Proc. Joint International Workshop on Ultra Wideband Systems & IEEE Conference on Ultra Wideband Systems and Technologies 2004, May 2004.
89 T. Terada, S. Yoshizumi, Y. Sanada, and T. Kuroda,
"Transceiver Circuits for Pulse-Based Ultra-WideBand,"
in Proc. IEEE International Symposium on Circuits and Systems (ISCAS’04),
pp. 4349-4352, May 2004.
pdf
88 黒田忠広,
"多層チップ間の無線データ通信を可能にする新技術を提案,"
SoC/SiPディべロッパーズ・コンファレンス2004, pp. B4/1-B4/21, May 2004.
87 D. Mizoguchi, Y.Yusof, N. Miura, T. Sakurai, and T. Kuroda,
"A 1.2Gb/s/pin Wireless Superconnect Based on Inductive Inter-Chip Signaling,"
電子情報通信学会技報, vol. 104, no. 67, ICD2004-23~36, pp. 31-36, May 2004.
86 寺田 崇秀, 善積 真吾, 黒田 忠広,
"Ultra-Wideband無線通信用送受信回路に関する研究,"
第一回 シリコンアナログRF研究会, Apr. 2004.
85 D. Mizoguchi, Y.Yusof, N. Miura, T. Sakurai, and T. Kuroda,
"A 1.2Gb/s/pin Wireless Superconnect Based on Inductive Inter-Chip Signaling,"
電気学会ULSIインターコネクト材料技術調査専門委員会, Mar. 2004.
84 D. Mizoguchi, Y.Yusof, N. Miura, T. Sakurai, and T. Kuroda,
"A 1.2Gb/s/pin Wireless Superconnect Based on Inductive Inter-Chip Signaling,"
ISSCC2004報告会, Mar. 2004.
83 D. Mizoguchi, Y. B. Yusof, N. Miura, T. Sakurai, and T. Kuroda,
"A 1.2Gb/s/pin Wireless Superconnect based on Inductive Inter-chip Signaling (IIS),"
IEEE International Solid-State Circuits Conference (ISSCC'04), Dig. Tech. Papers, pp. 142-143, Feb. 2004.
pdf
82 N. Miura, N. Kato, and T. Kuroda,
"Practical methodology of post-layout gate sizing for 15% more power saving,"
in Proc. ACM Asia and South Pacific Design Automation Conference (ASPDAC'04), pp. 434-437, Jan. 2004.
pdf
81

黒田忠広,
"{デバイス・実装・回路・システム} 総合設計,"
電子情報技術産業協会極限CMOS専門委員会, Nov. 2003.

80 S. Yoshizumi, T. Terada, J. Furukawa, Y. Sanada, and T. Kuroda,
"All Digital Transmitter Scheme and Transceiver Design for Pulse-Based Ultra-Wideband Radio,"
IEEE Ultra Wideband Systems and Technologies (UWBST’03), pp. 438-442, Nov. 2003.
pdf
79 H. Tsuda, T. Nakahara, Y. Mizutani and T. Kuroda,
"High-speed on-chip and inter-chip optical interconnect technology for Tbit/s communication,"
the 87th OSA Annual Meeting, WI1, Oct. 5-9, 2003.
pdf
78 T. Kuroda,
"10 Tips for Low Power CMOS Design,"
in Proc. ACM Design Automation Conference (DAC’03), tutorial, June 2003.
pdf
77 神田 浩一, ダナルドノ ドゥイ アントノ, 石田 光一, 川口 博, 黒田 忠広, 桜井 貴康,
"1.27Gb/s/pin 3mW/pin Wireless Superconnect (WSC) Interface Scheme,"
電子情報通信学会 集積回路研究会, May 2003.
76 T. Kuroda,
"Future Mobile Phones: A Beautiful Dream or Smoke in LSI Technology,"
IEEE International Solid-State Circuits Conference (ISSCC'03),
panel discussion, pp. 292-293, Feb. 2003.
pdf
75 K. Kanda, D. D. Antono, K. Ishida, H. Kawaguchi, T. Kuroda, and T. Sakurai,
"1.27-Gbps/pin, 3mW/pin Wireless Superconnect (WSC) Interface Scheme,"
IEEE International Solid-State Circuits Conference (ISSCC'03), pp. 186-187, Feb. 2003.
pdf
74 T. Kuroda,
"Will SOI ever become a mainstream technology?,"
IEEE International Electron Devices Meeting (IEDM’02),
Dig. Tech. Papers, panel discussion, p. 609, Dec. 2002.
pdf
73 黒田忠広,
"RF Microelectronics,"
REALIZEマイクロ波基礎講座, Sep. 2002.
72

黒田忠広,
"システムLSI-未来社会を創る-,"
トヨタ東富士研究所「FC21トーク」, Sep. 2002.

71 黒田忠広,
"半導体CMOSの低消費電力化,"
超伝導ニュース第50号, Sep. 2002.
pdf
70 T. Kuroda,
"UWB (Ultra-Wideband) - Great transformation in centennial anniversary of wireless communications -,"
CIAJ Journal, pp. 18-22, July 2002.
pdf
69 T. Kuroda,
"CICC 2002 Report,"
Electronic Journal, pp. 74-75, June 2002.
pdf
68 黒田忠広,
"Mooreの法則の限界 PCではない新しい目標から,"
Electronic Journal, p. 39, Apr. 2002.
67 T. Kuroda,
"CMOS design challenges to power wall (plenary),"
International Microprocesses and Nanotechnology Conference, Dig. Tech. Papers, pp. 6-7, Oct. 2001.
pdf
66 T. Kuroda,
"超低電力高性能携帯情報端末実現に向けた半導体集積回路技術,"
International Conference on Solid State Devices and Materials (SSDM’01) Short Course B, Sep. 2001.
65 T. Kuroda,
"Low power CMOS design challenges,"
IEICE Trans. Electronics, vol. E84-C, no. 8, pp. 1021-1028, Aug. 2001.
pdf
64 黒田忠広,
"総論-システムLSIの可能性と課題-,"
電子情報通信学会誌, vol. 84, no. 8 pp. 552-558, Aug. 2001.
pdf
63 T. Kuroda,
"2001 IEEE Symposium on VLSI Circuits Report,"
Electronic Journal, pp. 86-87, Jul. 2001.
62 T. Kuroda,
"2001 CICC Report,"
Electronic Journal, pp. 86-87, Jul. 2001.
pdf
61 K. Agawa, H. Hara, T. Takayanagi, and T. Kuroda,
"A bit-line leakage compensation scheme for low-voltage SRAM’s,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 36, no. 5, May 2001.
pdf
60 M. Hamada, Y. Ootaguro, and T. Kuroda,
"Utilizing surplus timing for power reduction,"
in Proc. IEEE Custom Integrated Circuits Conference (CICC’01), pp. 89-92, May 2001.
pdf
59 黒田忠広,
"低消費電力・高速VLSI設計,"
REALIZE理工学院, pp. 1-177, Jan. 2001.
58 R. Inanami, S. Magoshi, S. Kousai, M. Hamada, T. Takayanagi, K. Sugihara, K. Okumura, and T. Kuroda,
"Throughput enhancement strategy of maskless electron beam direct writing for logic device,"
IEEE International Electron Devices Meeting (IEDM 2000), Dig. Tech. Papers, 36.2, Dec. 2000.
pdf
57 T. Kuroda, T. Fujita, F. Hatori, T. Sakurai,
"Variable threshold-voltage CMOS technology,"
IEICE Trans. on Electronics, vol. E83C, no. 11, pp.1705-1715, Nov. 2000.
pdf
56 M. Takahashi, T. Nishikawa, M. Hamada, T. Takayanagi, H. Arakida, N. Machida, H. Yamamoto, T. Fujiyoshi, Y. Ohashi, O. Yamagishi, T. Samata, A. Asano, T. Terazawa, K. Ohmori, Y. Watanabe, H. Nakamura, S. Minami, T. Kuroda, and T. Furuyama,
"A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mbit embedded DRAM,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 35, no. 11, Nov. 2000.
pdf
55 黒田忠広,
"IT時代の集積回路の競争軸 低電力、低コスト、そして、短期開発,"
Electronic Journal, p. 39, Oct. 2000.
54 T. Kuroda,
"CICC 2000 Report,"
Electronic Journal, pp. 76-77, July 2000.
53 K. Agawa, H. Hara, T. Takayanagi, and T. Kuroda,
"A bit-line leakage compensation scheme for low-voltage SRAM’s,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. 70-71, June 2000.
pdf
52 T. Kuroda and M. Hamada,
"Low-power CMOS digital design with dual embedded adaptive power supplies,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 35, no. 4, pp. 652-655, Apr. 2000.
pdf
51 T. Nishikawa, M. Takahashi, M. Hamada, T. Takayanagi, H. Arakida, N. Machida, H. Yamamoto, T. Fujiyoshi, Yoko Matsumoto, O. Yamagishi, T. Samata, A. Asano, T. Terazawa, K. Ohmori, J. Shirakura, Y. Watanabe, H. Nakamura, S. Minami, T. Kuroda, and T. Furuyama,
"A 60MHz 240mW MPEG-4 video-phone LSI with 16Mbit embedded DRAM,"
IEEE International Solid-State Circuits Conference (ISSCC'00), Dig. Tech. Papers, pp. 230-231, Feb. 2000.
pdf
50 黒田忠広,
"超低電力消費LSI設計へ向けた技術動向と課題に関して,"
日本テクノセンター, pp. 1-28, Oct. 1999.
49 F. Ichiba, K. Suzuki, S. Mita, T. Kuroda, and T. Furuyama,
"Variable supply-voltage scheme with 95%-efficiency DC-DC converter for MPEG-4 codec,"
in Proc. IEEE International Symposium on Low Power Electronics and Design (ISLPED’99), pp. 54-59, Aug. 1999.
pdf
48

黒田忠広,
"デープサブミクロン時代の半導体集積回路の技術課題とEDAへの期待(招待論文),"
情報処理学会論文誌,vol. 40, no. 4, pp. 1500-1506, Apr. 1999.

pdf
47 M. Hamada, T. Terazawa, T. Higashi, S. Kitabayashi, S. Mita, Y. Watanabe, M. Ashino, H. Hara, and T. Kuroda,
"Flip-flop Selection Technique for Power-delay Trade-off,"
IEEE International Solid-State Circuits Conference (ISSCC'99), Dig. Tech. Papers, pp. 270-271, Feb. 1999.
pdf
46 M. Takahashi, M. Hamada, T. Nishikawa, H. Arakida, T. Fujita, F. Hatori, S. Mita, K. Suzuki, A. Chiba, T. Terasawa, F. Sano, Y. Watanabe, K. Usami, M. Igarashi, T. Ishikawa, M. Kanazawa, T. Kuroda, and T. Furuyama,
"A 60mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 33, no. 11, pp. 1772-1780, Nov. 1998.
pdf
45 黒田忠広,
"Low Power CMOS LSI Design Techniques,"
日本テクノセンター, pp. 1-32, Oct. 1998.
44 T. Kuroda,
"Low Power CMOS LSI Design Techniques,"
ISS Seminar, pp. 1-53, Sep. 1998.
43 M. Hamada, M. Takahashi, H. Arakida, A. Chiba, T. Terazawa, T. Ishikawa, M. Kanazawa, M. Igarashi, K. Usami, and T. Kuroda,
"A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme,"
in Proc. IEEE Custom Integrated Circuits Conference (CICC’98), pp. 495-498, May 1998.
pdf
42 T. Kuroda, K. Suzuki, S. Mita, T. Fujita, F. Yamane, F. Sano, A. Chiba, Y. Watanabe, K. Matsuda, T. Maeda, T. Sakurai, and T. Furuyama,
"Variable supply-voltage scheme for low-power high-speed CMOS digital design,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 33, no. 3, pp. 454-462, Mar. 1998.
pdf
41 M. Takahashi, M. Hamada, T. Nishikawa, H. Arakida, Y. Tsuboi, T. Fujita, F. Hatori, S. Mita, K. Suzuki, A. Chiba, T. Terasawa, F. Sano, Y. Watanabe, H. Momose, K. Usami, M. Igarashi, T. Ishikawa, M. Kanazawa, and T. Kuroda,
"A 60mW MPEG4 Video Codec Using Clustered Voltage Scaling with Variable Supply-voltage Scheme,"
IEEE International Solid-State Circuits Conference (ISSCC'98), Dig. Tech. Papers, pp. 36-37, Feb. 1998.
pdf
40 桜井貴康, 黒田忠広,
"低電力CMOS LSI技術,"
ISS産業科学システムズ, pp. 1-33, Jan. 1998.
39 桜井貴康, 黒田忠広,
"LSIの低消費電力化技術と最新動向,"
日本テクノセンター, pp. 1-39, Dec. 1997.
38 黒田忠広,
"低電力LSIの回路技術,"
日本工業技術センター, pp. 38-60, Sep. 1997.
37 K. Suzuki, S. Mita, T. Fujita, F. Yamane, F. Sano, T. Sakurai, A. Chiba, Y. Watanabe, K. Matsuda, T. Maeda, and T. Kuroda,
"A 300MIPS/W RISC core processor with variable supply-voltage scheme in variable threshold-voltage CMOS,"
in Proc. IEEE Custom Integrated Circuits Conference (CICC’97), pp. 587-590, May 1997.
pdf
36 黒田忠広, 桜井貴康,
"マルチメディアCMOS VLSIのための低電力回路設計技術(招待論文),"
電子情報通信学会論文誌A, vol. J80-A, no. 5, pp. 746-752, May 1997.
pdf
35 桜井貴康, 黒田忠広,
"マルチメディアLSIのための低消費電力回路設計技術,"
ISS産業科学システムズ, Apr. 1997.
34 黒田忠広,
"しきい値電圧可変技術とその応用,"
日本工業技術センター, pp. 42-69, Jan. 1997.
33 桜井貴康, 黒田忠広,
"LSIの低消費電力化・高速化技術,"
日本テクノセンター, pp. 1-44, Dec. 1996.
32 T. Kuroda, T. Fujita, S. Mita, T. Nagamatu, S. Yoshioka, K. Suzuki, F. Sano, M. Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakumu, and T. Sakurai,
"A 0.9V 150MHz 10mW 4mm2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 31, no. 11, pp. 1770-1779, Nov. 1996.
pdf
31 T. Sakurai and T. Kuroda,
"Low-power circuit design for multimedia CMOS VLSI’s,"
in Proc. Synthesis and System Integration of Mixed Technologies (SASIMI’96), pp. 3-10, Nov. 1996.
30 T. Kuroda and T. Sakurai,
"Threshold-Voltage Control Schemes through Substrate-Bias for Low-Power High-Speed CMOS LSI Designs,"
Journal of VLSI Signal Processors, vol. 13, no. 2/3, pp. 191-201, Aug. 1996.
pdf
29 T. Kuroda, T. Fujita, S. Mita, T. Mori, K. Matsuo, M. Kakumu, and T. Sakurai,
"Substrate noise influence on circuit performance in variable threshold-voltage scheme,"
in Proc. IEEE International Symposium on Low Power Electronics and Design (ISLPED’96), pp. 309-312, Aug. 1996.
pdf
28 黒田忠広,
"低消費電力/高速CMOS回路設計手法,"
日本工業技術センター, pp. 1-23, Aug. 1996.
27 黒田忠広,
"しきい値可変技術(VTCMOS)の回路技術と応用設計,"
日本工業技術センター, pp. 24-44, Aug. 1996.
26 K. Suzuki, T. Kuroda, T. Fujita, S. Mita, T. Nagamatsu, S. Yoshioka, F. Sano, M. Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakumu, and T. Sakurai,
"A 0.9V 150MHz 10mW 4mm2 2-D discrete cosine transform core processor with variable-threshold-voltage (VT) scheme,"
in Proc. 4th International Workshop on Advanced LSI’s, pp. 150-158, July 1996.
25 桜井貴康, 黒田忠広,
"マルチメディアLSIと低消費電力設計技術(招待),"
電気学会 第43回半導体専門講座, pp. 1-32, July 1996.
24 T. Kuroda, T. Fujita, M. Noda, Y. Itabashi, S. Kabumoto, T. S. Wong, D. Beeson, and D. Gray,
"Capacitor-free level-sensitive active pull-down ECL circuit with self-adjusting driving capability,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 31, no. 6, pp. 819-827, June 1996.
pdf
23 K. Seki, Y. Unekawa, K. Sakue, T. Nakano, S. Yoshida, T. Nagamatsu, H. Nakakita, Y. Kaneko, M. Motoyama, Y. Ohba, K. Ise, M. Ono, K. Fujikawara, Y. Miyazawa, T. Kuroda, Y. Kamatani, T. Sakurai, and A. Kanuma,
"A 5Gb/s ATM Switch Element CMOS LSI Supporting 5 Quality-of-Service Classes with 200MHz LVDS Interface,"
Technical Report of IEICE, ED96-51, pp. 57-64, June 1996.
22 藤田哲也, 黒田忠広, 三田真二, 永松 徹, 吉岡晋一, 佐野文彦, 法島政之, 室田雅之, 加古真琴, 衣川正明, 各務正一, 桜井貴康,
"A 0.9V 150MHz 10mW 4mm2 2-D Discrete Cosine Transform Core Professor with Variable-Threshold-Voltage(VT) Scheme,"
電子情報通信学会 集積回路研究会 信学技法, ED96-49/SDM96-32/ICD96-52, pp. 43-48, June 1996.
21 Transform Core Professor with Variable-Threshold-Voltage (VT) Scheme,
電子情報通信学会 集積回路研究会 信学技法, ED96-49/SDM96-32/ICD96-52, pp. 43-48, June 1996.
20 T. Kuroda, T. Fujita, T. Nagamatu, S. Yoshioka, T. Sei, K. Matsuo, Y. Hamura, T. Mori, M. Murota, M. Kakumu, and T. Sakurai,
"A High-Speed Low-Power 0.3um CMOS Gate Array with Variable Threshold
Voltage (VT) Scheme,"
in Proc. IEEE Custom Integrated Circuits Conference (CICC’96), pp. 53-56, May 1996.
pdf
19 黒田忠広,
"低消費電力化設計手法,"
日本工業技術センター, pp. 1-29, May 1996.
18 Y. Unekawa, K. Fukuda, K. Sakaue, T. Nakao, S. Yoshioka, T. Nagamatsu, H. Nakakita, Y. Kaneko, M. Motoyama, Y. Ohba, K. Ise, M. Ono, K. Fujiwara, Y. Miyazawa, T. Kuroda, Y. Kamitani, T. Sakurai, and A. Kanuma,
"A 5Gb/s 8 x 8 ATM Switch Element CMOS LSI Supporting Five Quality-of-Service Classes with 200MHz LVDS Interface,"
IEEE International Solid-State Circuits Conference (ISSCC'96), Dig. Tech. Papers, pp. 118-119, Feb. 1996.
pdf
17 T. Kuroda, T. Fujita, S. Mita, T. Nagamatu, S. Yoshioka, F. Sano, M. Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakumu, and T. Sakurai,
"A 0.9V 150MHz 10mW 4mm2 2-D Discrete Cosine Transform Core Processor with Variable-Threshold-Voltage Scheme,"
IEEE International Solid-State Circuits Conference (ISSCC'96), Dig. Tech. Papers, pp. 166-167, Feb. 1996.
pdf
16 黒田忠広,
"低消費電力設計手法,"
日本工業技術センター, pp. 35-53, Nov. 1995.
15 T. Kuroda and T. Sakurai,
"Overview of low-power ULSI circuit techniques,"
IEICE Transactions. on Electronics, vol. E78-C, no. 4, pp. 334-344, Apr. 1995.
pdf
14 K. Seta, H. Hara, T. Kuroda, M. Kakumu, and T. Sakurai,
"50% Active Power Saving without Speed Degradation Using Standby Power Reduction (SPR) Circuit,"
IEEE International Solid-State Circuits Conference (ISSCC'95), Dig. Tech. Papers, pp. 318-319, Feb. 1995.
pdf
13 T. Kuroda, T. Fujita, Y. Itabashi, S. Kabumoto, M. Noda, and A. Kanuma,
"1.65Bb/s 60mW 4:1 Multiplexer and 1.8Gb/s 80mW 1:4 Demultiplexer ICs Using 2V 3-level Series Gating ECL Circuits,"
IEEE International Solid-State Circuits Conference (ISSCC'95), Dig. Tech. Papers, pp. 36-37, Feb. 1995.
pdf
12 黒田忠広,
"ローパワーLSI設計技術の現状と動向,"
日本工業技術センター, pp. 1-24, Nov. 1994.
11 黒田忠広,
"ランダムロジック-パストランジスタロジック-,"
日本工業技術センター, pp. 25-38, Nov. 1994.
10 T. Kuroda, Y. Sakata, and K. Matsuo,
"Analysis and optimization of BiCMOS gate circuits,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 29, no. 5, pp. 564-571, May 1994.
pdf
9 T. Kuroda, T. Fujita, M. Noda, P. Thai, L. Yang, and D. Gray,
"Capacitor-free level-sensitive active pull-down ECL circuit with self-adjusting driving capability,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. 29-30, June 1993.
pdf
8 D. Gray, D. Beeson, B. Davis, D. Hutchings, P. Thai, T. S. Wong, T. Kuroda, M. Nakamura, and M. Noda,
"A 51k-gate low power ECL gate array family with metal-compiled and embedded SRAM,"
in Proc. IEEE Custom Integrated Circuits Conference (CICC’93), pp. 23.4.1-23.4.4, May 1993.
pdf
7 T. Kuroda, T. Fukunaga, K. Matsuo, K. Kasai, A. Hirata, S. Fujii, M. Kimura, and H. Suzuki,
"Automated Bias Control (ABC) circuit for high-performance VLSI's,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 27, no. 4, pp. 641-648, Apr. 1992.
pdf
6 H. Hara, T. Sakurai, T. Nagamatsu, S. Kobayashi, K. Seta, H. Momose, Y. Niitsu, H. Miyakawa, T. Kuroda, K. Matsuda, Y. Watanabe, F. Sano, and A. Chiba,
"0.5um BiCMOS Standard-Cell Macros Including 0.5W 3ns Register File and 0.6W 5ns 32kB Cache,"
IEEE International Solid-State Circuits Conference (ISSCC'92), Dig. Tech. Papers, pp. 46-47, Feb. 1992.
pdf
5 T. Kuroda, Y. Sakata, and K. Matsuo,
"Analysis and optimization of BiCMOS gate circuits,"
in Proc. IEEE International Symposium on Circuits and Systems (ISCAS’91), pp. 2112-2115, June 1991.
4 T. Kuroda, T. Fukunaga, K. Matsuo, K. Kasai, A. Hirata, S. Fujii, M. Kimura, and H. Suzuki,
"Automated Bias Control (ABC) circuit for high-performance VLSIs,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. 15-16, June 1991.
pdf
3 T. Kuroda, H. Suzuki, H. Akiba, T. Aoki, T. Shigematsu, and K. Kawagai,
"Unified design methodology and device architecture for multi-generation ASIC applications,"
in Proc. IEEE Custom Integrated Circuits Conference (CICC’88), pp. 25.7.1-25.7.4, May 1988.
pdf
2 G. Buurma, P. Michel, and T. Kuroda,
"A high performance scalable standard cell library with true second sourcing,"
Proc. IEEE Custom Integrated Circuits Conference (CICC’87), pp. 241-244, May 1987.
1 T. Kuroda, H. Akiba, H. Suzuki, and T. Aoki,
"P-well/N-well compatible CMOS processing for ASIC applications,"
International Conference on Solid State Devices and Materials (SSDM’86), Dig. Tech. Papers, pp. 57-60, Aug. 1986.