発表 Publication

論文一覧(2017年度)

14 程超然, 宮田知輝, 門本淳一郎, 天野英晴, 黒田忠広,
"ThruChip Interfaceを用いたバスにおける衝突検知,"
情報処理学会 全国大会, Mar. 2018.
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13 柴康太, 宮田知輝, 門本淳一郎, 天野英晴, 黒田忠広,
"ThruChip Interfaceの設計自動化,"
情報処理学会 全国大会, Mar. 2018.
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12 松下悠亮, 小島拓也, 門本淳一郎, 黒田忠広, 天野英晴,
"マルチコア積層システムCube-2の実装と評価,"
情報処理学会 全国大会, Mar. 2018.
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11 門本淳一郎, 宮田知輝, 天野英晴, 黒田忠広,
"ThruChip Interfaceを用いたコア間ネットワーク,"
情報処理学会 全国大会, Mar. 2018.
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10 天野英晴, 宇佐美公良, 黒田忠広, 近藤正章, 中村宏, 並木美太郎, 松谷宏紀,
"ビルディングブロック型計算システムプロジェクトの報告,"
情報処理学会 全国大会, Mar. 2018.
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9 植吉晃大, 安藤洸太, 廣瀨一俊, 高前田伸也, 門本淳一郎, 宮田知輝, 濱田基嗣, 黒田忠広, 本村真人,
"QUEST: A 7.49TOPS Multi-Purpose Log-Quantized DNN Inference Engine
Stacked on 96MB 3D SRAM Using Inductive-Coupling Technology in 40nm
CMOS,"
IEEE SSCS Japan Chapter/Kansai Chapter Technical Seminar, Feb. 2018.
8 K. Ueyoshi, K. Ando, K. Hirose, S. Takamaeda-Yamazaki, J. Kadomoto, T.
Miyata, M. Hamada, T. Kuroda, and M. Motomura,
"QUEST: A 7.49TOPS Multi-Purpose Log-Quantized DNN Inference Engine
Stacked on 96MB 3D SRAM Using Inductive-Coupling Technology in 40nm
CMOS,"
IEEE International Solid-State Circuits Conference (ISSCC'18), Dig. Tech. Papers, pp. 216-217, Feb. 2018.
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7 Akio Nomura, Yusuke Matsushita, Junichiro Kadomoto, Hiroki Matsutani,
Tadahiro Kuroda, and Hideharu Amano,
"Escalator Network for a 3D Chip Stack with Inductive Coupling
ThruChip Interface,"
International Journal of Networking and Computing, vol. 8, no. 1, pp.
124-139, Jan. 2018.
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6 A. Nomura, J. Kadomoto, T. Kuroda, and H. Amano,
"A practical collision avoidance method for an inter-chip bus with wireless
inductive Through Chip Interface,"
International Symposium on Computing and Networking (CANDAR'17),
Conference Paper, Nov. 2017.
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5 J. Kadomoto, H. Amano, and T. Kuroda,
"An Inductive-Coupling Link for 3-D Network-on-Chips,"
14th International SoC Design Conference (ISOCC 2017), Proceedings, pp. 150-151, Nov. 2017.
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4 S. Yanagawa, R. Shimizu, M. Hamada, T. Shimizu, and T. Kuroda,
"Wireless Power Transfer to Stacked Modules for IoT Sensor Nodes,"
14th International SoC Design Conference (ISOCC 2017), Proceedings, pp. 59-60, Nov. 2017.
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3 R. Shimizu, S. Yanagawa, T. Shimizu, M. Hamada, and T. Kuroda,
"Convolutional Neural Network for Industrial Egg Classification,"
14th International SoC Design Conference (ISOCC 2017), Proceedings, pp. 67-68, Nov. 2017.
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2 K. Ando, K. Ueyoshi, K. Orimo, H. Yonekawa, S. Sato, H. Nakahara, M. Ikebe, T. Asai, S. Takamaeda-Yamazaki, T. Kuroda, and M. Motomura,
"BRein Memory: A 13-Layer 4.2 K Neuron/0.8 M Synapse Binary/Ternary Reconfigurable In-Memory Deep Neural Network Accelerator in 65 nm CMOS,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. C24-C25, June 2017.
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1 M. Haraguchi, A. Kosuge, T. Igarashi, S. Masaki, M. Sueda, M. Hamada, and T. Kuroda,
"A 6Gb/s Rotatable Non-Contact Connector with High-Speed/I2C/CAN/SPI Interface Bridge IC,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. C150-C151, June 2017.
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