|8||K. Ueyoshi , K. Ando , K. Hirose, S. Takamaeda-Yamazaki, M. Hamada, T. Kuroda, and M. Motomura,
"QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3D SRAM Using Inductive Coupling Technology in 40-nm CMOS,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 54, no. 1, pp. 186-196, Jan. 2019.
|7||R. Shimizu, K. Asako, H. Ojima, S. Morinaga, M. Hamada, and T. Kuroda,
"Balanced Mini-batch Training for Imbalanced Image Data Classification with Neural Network,"
First IEEE International Conference on Artificial Intelligence for Industries (ai4i 2018), Proceedings, pp. 27-30, Sep. 2018.
|6||S. Yanagawa, R. Shimizu, M. Hamada and T. Kuroda,
"Wireless Power Transfer System for 3-D stacked Multiple Receivers Switching between Single and Dual Frequency Modes,"
IEEE International Midwest Symposium on Circuits and Systems, pp. 1046-1049, Aug. 2018.
|5||T. Maruyama, M. Hamada, and T. Kuroda,
"Comparative Performance Analysis of Dual-Rail Domino Logic and CMOS Logic Under Near-Threshold Operation,"
IEEE International Midwest Symposium on Circuits and Systems, pp. 25-28, Aug. 2018.
|4||T. Fujimaki, Y. Toeda, M. Hamada, and T. Kuroda,
"An Electrically Small On-Chip Antenna Scaled down to One-Twentyfifth by One-Fiftieth of Wavelength,"
2018 IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting, Proceedings, July 2018.
|3||Y. Toeda, T. Fujimaki, M. Hamada, and T. Kuroda,
"Fully integrated OOK-powered pad-less deep sub-wavelength-sized 5-GHz RFID with on-chip antenna using adiabatic logic in 0.18μm CMOS,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. C27-C28, June 2018.
|2||S. Yanagawa, R. Shimizu, M. Hamada, T. Shimizu, and T. Kuroda,
"Design Methodology in Wireless Power Transfer System for 3-D Stacked Multiple Receivers,"
IEEE International Symposium on Circuits & Systems, May 2018.
|1||K. Ando, K. Ueyoshi, K. Orimo, H. Yonekawa, S. Sato, H. Nakahara, S.
Takamaeda-Yamazaki, M. Ikebe, T. Asai, T. Kuroda, and M. Motomura,
"BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep
Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W,"
IEEE Journal of Solid-State Circuits (JSSC), vol. 53, no. 4, pp. 983-994, Apr.